Show all tests READMEs in the docs Signed-off-by: Daniel Lim Wee Soong <weesoong.lim@gmail.com>
diff --git a/docs/conf.py b/docs/conf.py index e41a90e..b2dd3cd 100644 --- a/docs/conf.py +++ b/docs/conf.py
@@ -35,6 +35,11 @@ sys.path.insert(0, os.path.abspath('.')) from markdown_code_symlinks import LinkParser, MarkdownSymlinksDomain # noqa +from sphinx.highlighting import lexers +from pygments.lexers.hdl import VerilogLexer + +lexers['verilog'] = VerilogLexer(tabsize=2) + # -- General configuration ------------------------------------------------ # If your documentation needs a minimal Sphinx version, state it here.
diff --git a/docs/examples/dsp.rst b/docs/examples/dsp.rst index 408007b..0b043e8 100644 --- a/docs/examples/dsp.rst +++ b/docs/examples/dsp.rst
@@ -1,14 +1,20 @@ -.. DSP Based Example Tests - DSP === -.. toctree:: +.. some aliases for the included rst files to use - dsp/dsp_combinational.md - dsp/dsp_in_registered.md - dsp/dsp_out_registered.md - dsp/dsp_inout_registered.md - dsp/dsp_inout_registered_dualclk.md - dsp/dsp_partial_registered.md - dsp/dsp_modes.md +.. |fig60| replace:: ``Figure 60 - DFF`` +.. _fig60: /examples/vtr/primitive.html#classical-d-flip-flop-test + +.. |dsp_combinational| replace:: ``dsp_combinational`` +.. _dsp_combinational: #combinational-dsp + +The following shows some DSP-based examples. + +.. include:: ../../tests/dsp/dsp_combinational/README.rst +.. include:: ../../tests/dsp/dsp_partial_registered/README.rst +.. include:: ../../tests/dsp/dsp_in_registered/README.rst +.. include:: ../../tests/dsp/dsp_out_registered/README.rst +.. include:: ../../tests/dsp/dsp_inout_registered/README.rst +.. include:: ../../tests/dsp/dsp_inout_registered_dualclk/README.rst +.. include:: ../../tests/dsp/dsp_modes/README.rst
diff --git a/docs/examples/vtr-examples.rst b/docs/examples/vtr-examples.rst index aef1d74..c3c87f9 100644 --- a/docs/examples/vtr-examples.rst +++ b/docs/examples/vtr-examples.rst
@@ -3,11 +3,8 @@ Verilog to Routing ================== -Primitive Block Timing Modeling Tutorial ----------------------------------------- +The following shows some examples taken from the `Verilog to Routing documentation <https://docs.verilogtorouting.org>`_. .. toctree:: - - vtr/lutff-pair.md - vtr/full-adder.md - vtr/dff.md + vtr/primitive.rst + vtr/arch.rst \ No newline at end of file
diff --git a/docs/examples/vtr/arch.rst b/docs/examples/vtr/arch.rst new file mode 100644 index 0000000..750ee16 --- /dev/null +++ b/docs/examples/vtr/arch.rst
@@ -0,0 +1,8 @@ +Architecture Reference +====================== + +The following shows examples taken from the +`Architecture Reference section <https://docs.verilogtorouting.org/en/latest/arch/reference>`_ +in the `Verilog to Routing documentation <https://docs.verilogtorouting.org>`_. + +.. include:: ../../../tests/vtr/lutff-pair/README.rst \ No newline at end of file
diff --git a/docs/examples/vtr/primitive.rst b/docs/examples/vtr/primitive.rst new file mode 100644 index 0000000..0aa5545 --- /dev/null +++ b/docs/examples/vtr/primitive.rst
@@ -0,0 +1,9 @@ +Primitive Block Timing Modeling Tutorial +======================================== + +The following shows examples taken from the +`Primitive Block Timing Modeling Tutorial <https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#>`_ +in the `Verilog to Routing documentation <https://docs.verilogtorouting.org>`_. + +.. include:: ../../../tests/vtr/dff/README.rst +.. include:: ../../../tests/vtr/full-adder/README.rst \ No newline at end of file
diff --git a/docs/requirements.txt b/docs/requirements.txt index 4e1216a..ae4e343 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt
@@ -11,7 +11,7 @@ git+https://github.com/SymbiFlow/sphinxcontrib-markdown-symlinks.git#egg=markdown_code_symlinks # Verilog diagrams using Yosys + netlistsvg -git+https://github.com/SymbiFlow/sphinxcontrib-verilog-diagrams.git@dca04723ec07209bd7be3e883e780ca9dd4f271e#egg=sphinxcontrib-verilog-diagrams +sphinxcontrib-verilog-diagrams # Module diagrams symbolator
diff --git a/tests/dsp/dsp_combinational/README.rst b/tests/dsp/dsp_combinational/README.rst new file mode 100644 index 0000000..41fa675 --- /dev/null +++ b/tests/dsp/dsp_combinational/README.rst
@@ -0,0 +1,33 @@ +Combinational DSP ++++++++++++++++++ + +.. symbolator:: ../../tests/dsp/dsp_combinational/dsp_combinational.sim.v + +.. verilog-diagram:: ../../tests/dsp/dsp_combinational/dsp_combinational.sim.v + :type: netlistsvg + :module: DSP_COMBINATIONAL + +| + +.. no-license:: ../../tests/dsp/dsp_combinational/dsp_combinational.sim.v + :language: verilog + :caption: tests/dsp/dsp_combinational/dsp_combinational.sim.v + +.. no-license:: ../../tests/dsp/dsp_combinational/golden.model.xml + :language: xml + :caption: tests/dsp/dsp_combinational/golden.model.xml + +.. no-license:: ../../tests/dsp/dsp_combinational/golden.pb_type.xml + :language: xml + :caption: tests/dsp/dsp_combinational/golden.pb_type.xml + +Detection of combinational connections +************************************** + +* Output has combinational connection with input + +Blackbox detection +****************** + +* Model of the leaf ``pb_type`` is generated +* Leaf ``pb_type`` XML is generated
diff --git a/tests/dsp/dsp_in_registered/README.md b/tests/dsp/dsp_in_registered/README.md deleted file mode 100644 index c40ab3f..0000000 --- a/tests/dsp/dsp_in_registered/README.md +++ /dev/null
@@ -1,18 +0,0 @@ -# `dsp_in_registered` test - -Test for "DSP style" block with all inputs registered. - -The tests use model from [`fig42-dff`](FIXME) and -[`dsp_combinational`](../dsp_combinational/README.md) tests. - -## Detection of combinational connections - - - [ ] output has combinational connection with input - - [ ] `pack_pattern` defined on wire connections with `pack` attribute - -## Blackbox detection - - - [ ] model of the leaf `pb_type` is generated - - [ ] leaf `pb_type` XML is generated - - [ ] all dependency models and `pb_type`s are included in the output files -
diff --git a/tests/dsp/dsp_in_registered/README.rst b/tests/dsp/dsp_in_registered/README.rst new file mode 100644 index 0000000..59a1d94 --- /dev/null +++ b/tests/dsp/dsp_in_registered/README.rst
@@ -0,0 +1,37 @@ +DSP-style block with all inputs registered +++++++++++++++++++++++++++++++++++++++++++ + +This uses the model from |fig60|_ and the |dsp_combinational|_ module. + +.. symbolator:: ../../tests/dsp/dsp_in_registered/dsp_in_registered.sim.v + +.. verilog-diagram:: ../../tests/dsp/dsp_in_registered/dsp_in_registered.sim.v + :type: netlistsvg + :module: DSP_IN_REGISTERED + +| + +.. no-license:: ../../tests/dsp/dsp_in_registered/dsp_in_registered.sim.v + :language: verilog + :caption: tests/dsp/dsp_in_registered/dsp_in_registered.sim.v + +.. no-license:: ../../tests/dsp/dsp_in_registered/golden.model.xml + :language: xml + :caption: tests/dsp/dsp_in_registered/golden.model.xml + +.. no-license:: ../../tests/dsp/dsp_in_registered/golden.pb_type.xml + :language: xml + :caption: tests/dsp/dsp_in_registered/golden.pb_type.xml + +Detection of combinational connections +************************************** + +* Output has combinational connection with input +* ``pack_pattern`` defined on wire connections with ``pack`` attribute + +Blackbox detection +****************** + +* Model of the leaf ``pb_type`` is generated +* Leaf ``pb_type`` XML is generated +* All dependency models and ``pb_type``\ s are included in the output files
diff --git a/tests/dsp/dsp_inout_registered/README.md b/tests/dsp/dsp_inout_registered/README.md deleted file mode 100644 index b66befe..0000000 --- a/tests/dsp/dsp_inout_registered/README.md +++ /dev/null
@@ -1,20 +0,0 @@ -# `dsp_inout_registered` test - -Test for "DSP style" block with both input and output is registered (using a -single clock). - -The tests use model from [`fig42-dff`](FIXME) and -[`dsp_combinational`](../dsp_combinational/README.md) tests. - - -## Detection of combinational connections - - - [ ] output has combinational connection with input - - [ ] `pack_pattern` defined on wire connections with `pack` attribute - -## Blackbox detection - - - [ ] model of the leaf `pb_type` is generated - - [ ] leaf `pb_type` XML is generated - - [ ] all dependency models and `pb_type`s are included in the output files -
diff --git a/tests/dsp/dsp_inout_registered/README.rst b/tests/dsp/dsp_inout_registered/README.rst new file mode 100644 index 0000000..4d8a75d --- /dev/null +++ b/tests/dsp/dsp_inout_registered/README.rst
@@ -0,0 +1,37 @@ +DSP-style block with inputs and outputs registered (single clock) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +This uses the model from |fig60|_ and the |dsp_combinational|_ module. + +.. symbolator:: ../../tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v + +.. verilog-diagram:: ../../tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v + :type: netlistsvg + :module: DSP_INOUT_REGISTERED + +| + +.. no-license:: ../../tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v + :language: verilog + :caption: tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v + +.. no-license:: ../../tests/dsp/dsp_inout_registered/golden.model.xml + :language: xml + :caption: tests/dsp/dsp_inout_registered/golden.model.xml + +.. no-license:: ../../tests/dsp/dsp_inout_registered/golden.pb_type.xml + :language: xml + :caption: tests/dsp/dsp_inout_registered/golden.pb_type.xml + +Detection of combinational connections +************************************** + +* Output has combinational connection with input +* ``pack_pattern`` defined on wire connections with ``pack`` attribute + +Blackbox detection +****************** + +* Model of the leaf ``pb_type`` is generated +* Leaf ``pb_type`` XML is generated +* All dependency models and ``pb_type``\ s are included in the output files
diff --git a/tests/dsp/dsp_inout_registered_dualclk/README.md b/tests/dsp/dsp_inout_registered_dualclk/README.md deleted file mode 100644 index f5baa0e..0000000 --- a/tests/dsp/dsp_inout_registered_dualclk/README.md +++ /dev/null
@@ -1,19 +0,0 @@ -# `dsp_inout_registered_dualclk` test - -Test for "DSP style" block with both input and output is registered using -separate clocks. - -The tests use model from [`fig42-dff`](FIXME) and -[`dsp_combinational`](../dsp_combinational/README.md) tests. - -## Detection of combinational connections - - - [ ] output has combinational connection with input - - [ ] `pack_pattern` defined on wire connections with `pack` attribute - -## Blackbox detection - - - [ ] model of the leaf `pb_type` is generated - - [ ] leaf `pb_type` XML is generated - - [ ] all dependency models and `pb_type`s are included in the output files -
diff --git a/tests/dsp/dsp_inout_registered_dualclk/README.rst b/tests/dsp/dsp_inout_registered_dualclk/README.rst new file mode 100644 index 0000000..3426d6b --- /dev/null +++ b/tests/dsp/dsp_inout_registered_dualclk/README.rst
@@ -0,0 +1,38 @@ + +DSP-style block with inputs and outputs registered using separate clocks +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +This uses the model from |fig60|_ and the |dsp_combinational|_ module. + +.. symbolator:: ../../tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v + +.. verilog-diagram:: ../../tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v + :type: netlistsvg + :module: DSP_INOUT_REGISTERED_DUALCLK + +| + +.. no-license:: ../../tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v + :language: verilog + :caption: tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v + +.. no-license:: ../../tests/dsp/dsp_inout_registered_dualclk/golden.model.xml + :language: xml + :caption: tests/dsp/dsp_inout_registered_dualclk/golden.model.xml + +.. no-license:: ../../tests/dsp/dsp_inout_registered_dualclk/golden.pb_type.xml + :language: xml + :caption: tests/dsp/dsp_inout_registered_dualclk/golden.pb_type.xml + +Detection of combinational connections +************************************** + +* Output has combinational connection with input +* ``pack_pattern`` defined on wire connections with ``pack`` attribute + +Blackbox detection +****************** + +* Model of the leaf ``pb_type`` is generated +* Leaf ``pb_type`` XML is generated +* All dependency models and ``pb_type``\ s are included in the output files
diff --git a/tests/dsp/dsp_modes/README.md b/tests/dsp/dsp_modes/README.md deleted file mode 100644 index d0e25c7..0000000 --- a/tests/dsp/dsp_modes/README.md +++ /dev/null
@@ -1,39 +0,0 @@ -# `dsp_modes` test - -Test for "DSP style" block with multiple different modes. - -The modes possible are; - - * Combinational only - (IE [`dsp_combinational`](../dsp_combinational/README.md)). - - * Register on one input - (IE [`dsp_partial_registered`](../dsp_partial_registered/README.md)). - - * Register on all inputs - (IE [`dsp_in_registered`](../dsp_in_registered/README.md)). - - * Register on outputs - (IE [`dsp_out_registered`](../dsp_out_registered/README.md)). - - * Register on both inputs and outputs (with same clock) - (IE [`dsp_inout_registered`](../dsp_inout_registered/README.md)). - - * Register on both inputs and outputs (with independent clocks) - (IE [`dsp_inout_registered_dualclk`](../dsp_inout_registered_dualclk/README.md)). - - * Register on both inputs and outputs (with independent clocks) - (IE [`dsp_inout_registered_dualclk`](../dsp_inout_registered_dualclk/README.md)). - - -## Blackbox detection - - - [ ] model of the leaf `pb_type` is generated - - [ ] leaf `pb_type` XML is generated - - [ ] all dependency models and `pb_type`s are included in the output files - -## Modes generation - - - [ ] all the modes from list defined with `MODES` attribute - - [ ] mode setting is included in `pb_type` generation (correct part of logic is used) - - [ ] modes connections are generated correctly
diff --git a/tests/dsp/dsp_modes/README.rst b/tests/dsp/dsp_modes/README.rst new file mode 100644 index 0000000..df20b90 --- /dev/null +++ b/tests/dsp/dsp_modes/README.rst
@@ -0,0 +1,56 @@ +DSP-style block with different modes +++++++++++++++++++++++++++++++++++++ + +The possible modes are + +* Combinational only (i.e. |dsp_combinational|_) +* Register on one input (i.e. |dsp_partial_registered|_) +* Register on all inputs (i.e. |dsp_in_registered|_) +* Register on outputs (i.e. |dsp_out_registered|_). +* Register on both inputs and outputs (with same clock) (i.e. |dsp_inout_registered|_). + +.. |dsp_partial_registered| replace:: ``dsp_partial_registered`` +.. _dsp_partial_registered: #dsp-style-block-with-only-one-input-registered + +.. |dsp_in_registered| replace:: ``dsp_in_registered`` +.. _dsp_in_registered: #dsp-style-block-with-all-inputs-registered + +.. |dsp_out_registered| replace:: ``dsp_out_registered`` +.. _dsp_out_registered: #dsp-style-block-with-outputs-registered + +.. |dsp_inout_registered| replace:: ``dsp_inout_registered`` +.. _dsp_inout_registered: #dsp-style-block-with-inputs-and-outputs-registered-single-clock + +.. symbolator:: ../../tests/dsp/dsp_modes/dsp_modes.sim.v + +.. verilog-diagram:: ../../tests/dsp/dsp_modes/dsp_modes.sim.v + :type: netlistsvg + :module: DSP_MODES + +| + +.. no-license:: ../../tests/dsp/dsp_modes/dsp_modes.sim.v + :language: verilog + :caption: tests/dsp/dsp_modes/dsp_modes.sim.v + +.. no-license:: ../../tests/dsp/dsp_modes/golden.model.xml + :language: xml + :caption: tests/dsp/dsp_modes/golden.model.xml + +.. no-license:: ../../tests/dsp/dsp_modes/golden.pb_type.xml + :language: xml + :caption: tests/dsp/dsp_modes/golden.pb_type.xml + +Blackbox detection +****************** + +* Model of the leaf ``pb_type`` is generated +* Leaf ``pb_type`` XML is generated +* All dependency models and ``pb_type``\ s are included in the output files + +Modes generation +**************** + +* All the modes from list defined with ``MODES`` attribute +* Mode setting is included in ``pb_type`` generation (correct part of logic is used) +* Modes connections are generated correctly
diff --git a/tests/dsp/dsp_out_registered/README.md b/tests/dsp/dsp_out_registered/README.md deleted file mode 100644 index 27c46e2..0000000 --- a/tests/dsp/dsp_out_registered/README.md +++ /dev/null
@@ -1,19 +0,0 @@ -# `dsp_out_registered` test - -Test for "DSP style" block with outputs registered. - -The tests use model from [`fig42-dff`](FIXME) and -[`dsp_combinational`](../dsp_combinational/README.md) tests. - - -## Detection of combinational connections - - - [ ] output has combinational connection with input - - [ ] `pack_pattern` defined on wire connections with `pack` attribute - -## Blackbox detection - - - [ ] model of the leaf `pb_type` is generated - - [ ] leaf `pb_type` XML is generated - - [ ] all dependency models and `pb_type`s are included in the output files -
diff --git a/tests/dsp/dsp_out_registered/README.rst b/tests/dsp/dsp_out_registered/README.rst new file mode 100644 index 0000000..7e768ee --- /dev/null +++ b/tests/dsp/dsp_out_registered/README.rst
@@ -0,0 +1,37 @@ +DSP-style block with outputs registered ++++++++++++++++++++++++++++++++++++++++ + +This uses the model from |fig60|_ and the |dsp_combinational|_ module. + +.. symbolator:: ../../tests/dsp/dsp_out_registered/dsp_out_registered.sim.v + +.. verilog-diagram:: ../../tests/dsp/dsp_out_registered/dsp_out_registered.sim.v + :type: netlistsvg + :module: DSP_OUT_REGISTERED + +| + +.. no-license:: ../../tests/dsp/dsp_out_registered/dsp_out_registered.sim.v + :language: verilog + :caption: tests/dsp/dsp_out_registered/dsp_out_registered.sim.v + +.. no-license:: ../../tests/dsp/dsp_out_registered/golden.model.xml + :language: xml + :caption: tests/dsp/dsp_out_registered/golden.model.xml + +.. no-license:: ../../tests/dsp/dsp_out_registered/golden.pb_type.xml + :language: xml + :caption: tests/dsp/dsp_out_registered/golden.pb_type.xml + +Detection of combinational connections +************************************** + +* Output has combinational connection with input +* ``pack_pattern`` defined on wire connections with ``pack`` attribute + +Blackbox detection +****************** + +* Model of the leaf ``pb_type`` is generated +* Leaf ``pb_type`` XML is generated +* All dependency models and ``pb_type``\ s are included in the output files
diff --git a/tests/dsp/dsp_partial_registered/README.md b/tests/dsp/dsp_partial_registered/README.md deleted file mode 100644 index 7fd5d26..0000000 --- a/tests/dsp/dsp_partial_registered/README.md +++ /dev/null
@@ -1,18 +0,0 @@ -# `dsp_partial_registered` test - -Test for "DSP style" block with one input registered. - -The tests use model from [`fig42-dff`](FIXME) and -[`dsp_combinational`](../dsp_combinational/README.md) tests. - -## Detection of combinational connections - - - [ ] output has combinational connection with input - - [ ] `pack_pattern` defined on wire connections with `pack` attribute - -## Blackbox detection - - - [ ] model of the leaf `pb_type` is generated - - [ ] leaf `pb_type` XML is generated - - [ ] all dependency models and `pb_type`s are included in the output files -
diff --git a/tests/dsp/dsp_partial_registered/README.rst b/tests/dsp/dsp_partial_registered/README.rst new file mode 100644 index 0000000..e075bae --- /dev/null +++ b/tests/dsp/dsp_partial_registered/README.rst
@@ -0,0 +1,37 @@ +DSP-style block with only one input registered +++++++++++++++++++++++++++++++++++++++++++++++ + +This uses the model from |fig60|_ and the |dsp_combinational|_ module. + +.. symbolator:: ../../tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v + +.. verilog-diagram:: ../../tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v + :type: netlistsvg + :module: DSP_PARTIAL_REGISTERED + +| + +.. no-license:: ../../tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v + :language: verilog + :caption: tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v + +.. no-license:: ../../tests/dsp/dsp_partial_registered/golden.model.xml + :language: xml + :caption: tests/dsp/dsp_partial_registered/golden.model.xml + +.. no-license:: ../../tests/dsp/dsp_partial_registered/golden.pb_type.xml + :language: xml + :caption: tests/dsp/dsp_partial_registered/golden.pb_type.xml + +Detection of combinational connections +************************************** + +* Output has combinational connection with input +* ``pack_pattern`` defined on wire connections with ``pack`` attribute + +Blackbox detection +****************** + +* Model of the leaf ``pb_type`` is generated +* Leaf ``pb_type`` XML is generated +* All dependency models and ``pb_type``\ s are included in the output files
diff --git a/tests/vtr/dff/README.rst b/tests/vtr/dff/README.rst new file mode 100644 index 0000000..79ce265 --- /dev/null +++ b/tests/vtr/dff/README.rst
@@ -0,0 +1,48 @@ +Classical D-Flip-Flop test +++++++++++++++++++++++++++ + +An example of the classical D-Flip-Flop shown in |fig60|_. + +.. |fig60| replace:: ``Figure 60 - DFF`` +.. _fig60: https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#sequential-block-no-internal-paths + +.. image:: ../../../tests/vtr/dff/dff.svg + :alt: Figure 60 from Verilog to Routing Documentation + +*Fig. 60 - DFF* + +| + +.. symbolator:: ../../../tests/vtr/dff/dff.sim.v + +.. verilog-diagram:: ../../../tests/vtr/dff/dff.sim.v + :type: netlistsvg + :module: DFF + +| + +.. no-license:: ../../../tests/vtr/dff/dff.sim.v + :language: verilog + :caption: tests/vtr/dff/dff.sim.v + +.. no-license:: ../../../tests/vtr/dff/golden.model.xml + :language: xml + :caption: tests/vtr/dff/golden.model.xml + + +Clock associations inference +**************************** + +* Automatic inference is signal is associated with any clock and include the info in the model +* Automatic clock detection (signals named ``clk`` are considered as clocks) + +Blackbox detection +****************** + +* Model of the leaf ``pb_type`` is generated +* Leaf ``pb_type`` XML is generated + +Timings +******* + +* All the timings defined for wires with attributes should be included in ``pb_type`` XML
diff --git a/tests/vtr/dff/dff.sim.v b/tests/vtr/dff/dff.sim.v index 91c1c12..ed67b34 100644 --- a/tests/vtr/dff/dff.sim.v +++ b/tests/vtr/dff/dff.sim.v
@@ -7,6 +7,8 @@ * * SPDX-License-Identifier: ISC */ +`ifndef DFF +`define DFF (* whitebox *) module DFF (D, CLK, Q); @@ -57,3 +59,5 @@ `endif endmodule + +`endif \ No newline at end of file
diff --git a/tests/vtr/full-adder/README.rst b/tests/vtr/full-adder/README.rst new file mode 100644 index 0000000..8087fb6 --- /dev/null +++ b/tests/vtr/full-adder/README.rst
@@ -0,0 +1,51 @@ +Full Adder Example +++++++++++++++++++ + +An example of the classical combinational `"full adder" <https://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder>`_ circuit shown in |fig59|_. + +.. |fig59| replace:: ``Figure 59 - Full Adder`` +.. _fig59: https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#combinational-block + +.. image:: ../../../tests/vtr/full-adder/full-adder.svg + :alt: Figure 59 from Verilog to Routing Documentation + +*Fig. 59 - Full Adder* + +| + +.. symbolator:: ../../../tests/vtr/full-adder/adder.sim.v + +.. verilog-diagram:: ../../../tests/vtr/full-adder/adder.sim.v + :type: netlistsvg + :module: ADDER + +| + +.. no-license:: ../../../tests/vtr/full-adder/adder.sim.v + :language: verilog + :caption: tests/vtr/full-adder/adder.sim.v + +.. no-license:: ../../../tests/vtr/full-adder/golden.model.xml + :language: xml + :caption: tests/vtr/full-adder/golden.model.xml + +.. no-license:: ../../../tests/vtr/full-adder/golden.pb_type.xml + :language: xml + :caption: tests/vtr/full-adder/golden.pb_type.xml + + +Detection of combinational connections +************************************** + +* Output has combinational connection with input + +Blackbox detection +****************** + +* Model of the leaf ``pb_type`` is generated +* Leaf ``pb_type`` XML is generated + +Timings +******* + +* All the timings defined for wires with attributes should be included in ``pb_type`` XML
diff --git a/tests/vtr/lutff-pair/README.rst b/tests/vtr/lutff-pair/README.rst new file mode 100644 index 0000000..e6550a8 --- /dev/null +++ b/tests/vtr/lutff-pair/README.rst
@@ -0,0 +1,46 @@ +LUT with FlipFlop Example ++++++++++++++++++++++++++ + +An example of the classical LUT with FlipFlop pair shown in |fig31|_ demonstrating the `<pack_pattern>` tag. + +.. |fig31| replace:: ``Figure 31 - Pack Pattern Example`` +.. _fig31: https://docs.verilogtorouting.org/en/latest/arch/reference/#id35 + +.. image:: ../../../tests/vtr/lutff-pair/lutff-pair.png + :alt: Figure 31 from Verilog to Routing Documentation + +*Fig. 31 - Pack Pattern Example* + +| + +.. symbolator:: ../../../tests/vtr/lutff-pair/pair.sim.v + +.. .. verilog-diagram:: ../../../tests/vtr/lutff-pair/pair.sim.v +.. :type: netlistsvg +.. :module: PAIR + +| + +.. no-license:: ../../../tests/vtr/lutff-pair/pair.sim.v + :language: verilog + :caption: tests/vtr/lutff-pair/pair.sim.v + +.. no-license:: ../../../tests/vtr/lutff-pair/golden.model.xml + :language: xml + :caption: tests/vtr/lutff-pair/golden.model.xml + +.. no-license:: ../../../tests/vtr/lutff-pair/golden.pb_type.xml + :language: xml + :caption: tests/vtr/lutff-pair/golden.pb_type.xml + +Blackbox detection +------------------ + +* Model of the leaf ``pb_type`` is generated +* Leaf ``pb_type`` XML is generated +* All dependency models and ``pb_type``\ s are included in the output files + +Carry chain inference +--------------------- + +* ``pack_pattern`` inference - ``pack_pattern``\ s defined on wires with ``pack`` attributes should be propagated to ``pb_type`` XMLs