Added a test case for the NO_SEQ attribute Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/tests/no_seq/README.rst b/tests/no_seq/README.rst new file mode 100644 index 0000000..0ed53ae --- /dev/null +++ b/tests/no_seq/README.rst
@@ -0,0 +1,28 @@ +Forced non-sequential relations to an input ++++++++++++++++++++++++++++++++++++++++++++ + +There are cases when a primitive needs to have different input/output port relations that it can be inferred from its internal behavioral model. This is due to the way that VPR requires primitives to be modelled. + +V2X allows forcing certain inputs to have no sequential relations to any outputs. Such an input port need to be annotated using the `(* NO_SEQ *)` attribute. + +This example shows a LOGIC cell macro primitive that models a whole LOGIC cell of Quicklogic EOS S3 FPGA architecture. The primitive is defined according to `VTR documentation <https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#sequential-block-with-internal-paths-and-combinational-input>`_. + +.. symbolator:: logic_macro.sim.v + +.. verilog-diagram:: logic_macro.sim.v + :type: netlistsvg + :module: LOGIC_MACRO + +.. no-license:: logic_macro.sim.v + :language: verilog + :caption: tests/no_seq/logic_macro.sim.v + +Input ports annotated with the `(* NO_SEQ *)` attribute are combinationaly related to TZ and CZ outputs and sequentially related to the QZ output. According to the VPR documentation there should be no clock relation to them defined in the pb_type XML and this is what the `(* NO_SEQ *)` attribute ensures. + +.. literalinclude:: logic_macro.model.xml + :language: xml + :caption: logic_macro.model.xml + +.. literalinclude:: logic_macro.pb_type.xml + :language: xml + :caption: logic_macro.pb_type.xml
diff --git a/tests/no_seq/golden.model.xml b/tests/no_seq/golden.model.xml new file mode 100644 index 0000000..b373b38 --- /dev/null +++ b/tests/no_seq/golden.model.xml
@@ -0,0 +1,34 @@ +<models xmlns:xi="http://www.w3.org/2001/XInclude"> + <model name="LOGIC_MACRO"> + <input_ports> + <port combinational_sink_ports="QZ CZ" name="BA1"/> + <port combinational_sink_ports="QZ CZ" name="BA2"/> + <port combinational_sink_ports="QZ CZ" name="BAB"/> + <port combinational_sink_ports="QZ CZ" name="BB1"/> + <port combinational_sink_ports="QZ CZ" name="BB2"/> + <port combinational_sink_ports="QZ CZ" name="BSL"/> + <port combinational_sink_ports="FZ" name="F1"/> + <port combinational_sink_ports="FZ" name="F2"/> + <port combinational_sink_ports="FZ" name="FS"/> + <port is_clock="1" name="QCK"/> + <port clock="QCK" name="QDI"/> + <port clock="QCK" name="QDS"/> + <port clock="QCK" name="QEN"/> + <port clock="QCK" name="QRT"/> + <port clock="QCK" name="QST"/> + <port combinational_sink_ports="QZ CZ TZ" name="TA1"/> + <port combinational_sink_ports="QZ CZ TZ" name="TA2"/> + <port combinational_sink_ports="QZ CZ TZ" name="TAB"/> + <port combinational_sink_ports="QZ CZ TZ" name="TB1"/> + <port combinational_sink_ports="QZ CZ TZ" name="TB2"/> + <port combinational_sink_ports="QZ CZ" name="TBS"/> + <port combinational_sink_ports="QZ CZ TZ" name="TSL"/> + </input_ports> + <output_ports> + <port name="CZ"/> + <port name="FZ"/> + <port clock="QCK" name="QZ"/> + <port name="TZ"/> + </output_ports> + </model> +</models>
diff --git a/tests/no_seq/golden.pb_type.xml b/tests/no_seq/golden.pb_type.xml new file mode 100644 index 0000000..98fc5ec --- /dev/null +++ b/tests/no_seq/golden.pb_type.xml
@@ -0,0 +1,76 @@ +<?xml version='1.0' encoding='utf-8'?> +<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="LOGIC_MACRO" num_pb="1"> + <blif_model>.subckt LOGIC_MACRO</blif_model> + <clock name="QCK" num_pins="1"/> + <input name="BA1" num_pins="1"/> + <input name="BA2" num_pins="1"/> + <input name="BAB" num_pins="1"/> + <input name="BB1" num_pins="1"/> + <input name="BB2" num_pins="1"/> + <input name="BSL" num_pins="1"/> + <input name="F1" num_pins="1"/> + <input name="F2" num_pins="1"/> + <input name="FS" num_pins="1"/> + <input name="QDI" num_pins="1"/> + <input name="QDS" num_pins="1"/> + <input name="QEN" num_pins="1"/> + <input name="QRT" num_pins="1"/> + <input name="QST" num_pins="1"/> + <input name="TA1" num_pins="1"/> + <input name="TA2" num_pins="1"/> + <input name="TAB" num_pins="1"/> + <input name="TB1" num_pins="1"/> + <input name="TB2" num_pins="1"/> + <input name="TBS" num_pins="1"/> + <input name="TSL" num_pins="1"/> + <output name="CZ" num_pins="1"/> + <output name="FZ" num_pins="1"/> + <output name="QZ" num_pins="1"/> + <output name="TZ" num_pins="1"/> + <delay_constant in_port="BA1" max="1e-10" out_port="CZ"/> + <delay_constant in_port="BA2" max="1e-10" out_port="CZ"/> + <delay_constant in_port="BAB" max="1e-10" out_port="CZ"/> + <delay_constant in_port="BB1" max="1e-10" out_port="CZ"/> + <delay_constant in_port="BB2" max="1e-10" out_port="CZ"/> + <delay_constant in_port="BSL" max="1e-10" out_port="CZ"/> + <delay_constant in_port="TA1" max="1e-10" out_port="CZ"/> + <delay_constant in_port="TA2" max="1e-10" out_port="CZ"/> + <delay_constant in_port="TAB" max="1e-10" out_port="CZ"/> + <delay_constant in_port="TB1" max="1e-10" out_port="CZ"/> + <delay_constant in_port="TB2" max="1e-10" out_port="CZ"/> + <delay_constant in_port="TBS" max="1e-10" out_port="CZ"/> + <delay_constant in_port="TSL" max="1e-10" out_port="CZ"/> + <delay_constant in_port="F1" max="1e-10" out_port="FZ"/> + <delay_constant in_port="F2" max="1e-10" out_port="FZ"/> + <delay_constant in_port="FS" max="1e-10" out_port="FZ"/> + <T_setup clock="QCK" port="QDI" value="1e-10"/> + <T_hold clock="QCK" port="QDI" value="1e-10"/> + <T_setup clock="QCK" port="QDS" value="1e-10"/> + <T_hold clock="QCK" port="QDS" value="1e-10"/> + <T_setup clock="QCK" port="QEN" value="1e-10"/> + <T_hold clock="QCK" port="QEN" value="1e-10"/> + <T_setup clock="QCK" port="QRT" value="1e-10"/> + <T_setup clock="QCK" port="QST" value="1e-10"/> + <T_setup clock="QCK" port="QZ" value="1e-10"/> + <T_hold clock="QCK" port="QZ" value="1e-10"/> + <T_clock_to_Q clock="QCK" max="1e-10" port="QZ"/> + <delay_constant in_port="BA1" max="1e-10" out_port="QZ"/> + <delay_constant in_port="BA2" max="1e-10" out_port="QZ"/> + <delay_constant in_port="BAB" max="1e-10" out_port="QZ"/> + <delay_constant in_port="BB1" max="1e-10" out_port="QZ"/> + <delay_constant in_port="BB2" max="1e-10" out_port="QZ"/> + <delay_constant in_port="BSL" max="1e-10" out_port="QZ"/> + <delay_constant in_port="TA1" max="1e-10" out_port="QZ"/> + <delay_constant in_port="TA2" max="1e-10" out_port="QZ"/> + <delay_constant in_port="TAB" max="1e-10" out_port="QZ"/> + <delay_constant in_port="TB1" max="1e-10" out_port="QZ"/> + <delay_constant in_port="TB2" max="1e-10" out_port="QZ"/> + <delay_constant in_port="TBS" max="1e-10" out_port="QZ"/> + <delay_constant in_port="TSL" max="1e-10" out_port="QZ"/> + <delay_constant in_port="TA1" max="1e-10" out_port="TZ"/> + <delay_constant in_port="TA2" max="1e-10" out_port="TZ"/> + <delay_constant in_port="TAB" max="1e-10" out_port="TZ"/> + <delay_constant in_port="TB1" max="1e-10" out_port="TZ"/> + <delay_constant in_port="TB2" max="1e-10" out_port="TZ"/> + <delay_constant in_port="TSL" max="1e-10" out_port="TZ"/> +</pb_type>
diff --git a/tests/no_seq/logic_macro.sim.v b/tests/no_seq/logic_macro.sim.v new file mode 100644 index 0000000..0f2331e --- /dev/null +++ b/tests/no_seq/logic_macro.sim.v
@@ -0,0 +1,185 @@ +/* + * Copyright (C) 2020 The SymbiFlow Authors. + * + * Use of this source code is governed by a ISC-style + * license that can be found in the LICENSE file or at + * https://opensource.org/licenses/ISC + * + * SPDX-License-Identifier: ISC + */ + +(* whitebox *) +module LOGIC_MACRO (QST, QDS, TBS, TAB, TSL, TA1, TA2, TB1, TB2, BAB, BSL, BA1, BA2, BB1, BB2, QDI, QEN, QCK, QRT, F1, F2, FS, TZ, CZ, QZ, FZ); + + // =============== C_FRAG =============== + + (* NO_SEQ *) + input wire TBS; + (* NO_SEQ *) + input wire TAB; + (* NO_SEQ *) + input wire TSL; + (* NO_SEQ *) + input wire TA1; + (* NO_SEQ *) + input wire TA2; + (* NO_SEQ *) + input wire TB1; + (* NO_SEQ *) + input wire TB2; + (* NO_SEQ *) + input wire BAB; + (* NO_SEQ *) + input wire BSL; + (* NO_SEQ *) + input wire BA1; + (* NO_SEQ *) + input wire BA2; + (* NO_SEQ *) + input wire BB1; + (* NO_SEQ *) + input wire BB2; + + (* DELAY_CONST_TAB="1e-10" *) + (* DELAY_CONST_TSL="1e-10" *) + (* DELAY_CONST_TA1="1e-10" *) + (* DELAY_CONST_TA2="1e-10" *) + (* DELAY_CONST_TB1="1e-10" *) + (* DELAY_CONST_TB2="1e-10" *) + output wire TZ; + + (* DELAY_CONST_TBS="1e-10" *) + (* DELAY_CONST_TAB="1e-10" *) + (* DELAY_CONST_TSL="1e-10" *) + (* DELAY_CONST_TA1="1e-10" *) + (* DELAY_CONST_TA2="1e-10" *) + (* DELAY_CONST_TB1="1e-10" *) + (* DELAY_CONST_TB2="1e-10" *) + (* DELAY_CONST_BAB="1e-10" *) + (* DELAY_CONST_BSL="1e-10" *) + (* DELAY_CONST_BA1="1e-10" *) + (* DELAY_CONST_BA2="1e-10" *) + (* DELAY_CONST_BB1="1e-10" *) + (* DELAY_CONST_BB2="1e-10" *) + output wire CZ; + + // Control parameters + parameter [0:0] TAS1 = 1'b0; + parameter [0:0] TAS2 = 1'b0; + parameter [0:0] TBS1 = 1'b0; + parameter [0:0] TBS2 = 1'b0; + + parameter [0:0] BAS1 = 1'b0; + parameter [0:0] BAS2 = 1'b0; + parameter [0:0] BBS1 = 1'b0; + parameter [0:0] BBS2 = 1'b0; + + // Input routing inverters + wire TAP1 = (TAS1) ? ~TA1 : TA1; + wire TAP2 = (TAS2) ? ~TA2 : TA2; + wire TBP1 = (TBS1) ? ~TB1 : TB1; + wire TBP2 = (TBS2) ? ~TB2 : TB2; + + wire BAP1 = (BAS1) ? ~BA1 : BA1; + wire BAP2 = (BAS2) ? ~BA2 : BA2; + wire BBP1 = (BBS1) ? ~BB1 : BB1; + wire BBP2 = (BBS2) ? ~BB2 : BB2; + + // 1st mux stage + wire TAI = TSL ? TAP2 : TAP1; + wire TBI = TSL ? TBP2 : TBP1; + + wire BAI = BSL ? BAP2 : BAP1; + wire BBI = BSL ? BBP2 : BBP1; + + // 2nd mux stage + wire TZI = TAB ? TBI : TAI; + wire BZI = BAB ? BBI : BAI; + + // 3rd mux stage + wire CZI = TBS ? BZI : TZI; + + // Output + assign TZ = TZI; + assign CZ = CZI; + + // =============== Q_FRAG =============== + + (* CLOCK *) + input wire QCK; + + // Cannot model timing, VPR currently does not support async SET/RESET + (* SETUP="QCK 1e-10" *) + (* NO_COMB *) + input wire QST; + + // Cannot model timing, VPR currently does not support async SET/RESET + (* SETUP="QCK 1e-10" *) + (* NO_COMB *) + input wire QRT; + + (* SETUP="QCK 1e-10" *) + (* HOLD="QCK 1e-10" *) + (* NO_COMB *) + input wire QEN; + + (* SETUP="QCK 1e-10" *) + (* HOLD="QCK 1e-10" *) + (* NO_COMB *) + input wire QDI; + + (* SETUP="QCK 1e-10" *) + (* HOLD="QCK 1e-10" *) + (* NO_COMB *) + input wire QDS; + + (* CLK_TO_Q = "QCK 1e-10" *) + (* DELAY_CONST_TBS="1e-10" *) + (* DELAY_CONST_TAB="1e-10" *) + (* DELAY_CONST_TSL="1e-10" *) + (* DELAY_CONST_TA1="1e-10" *) + (* DELAY_CONST_TA2="1e-10" *) + (* DELAY_CONST_TB1="1e-10" *) + (* DELAY_CONST_TB2="1e-10" *) + (* DELAY_CONST_BAB="1e-10" *) + (* DELAY_CONST_BSL="1e-10" *) + (* DELAY_CONST_BA1="1e-10" *) + (* DELAY_CONST_BA2="1e-10" *) + (* DELAY_CONST_BB1="1e-10" *) + (* DELAY_CONST_BB2="1e-10" *) + (* SETUP="QCK 1e-10" *) + (* HOLD="QCK 1e-10" *) + output reg QZ; + + // Parameters + parameter [0:0] Z_QCKS = 1'b1; + + // The QZI-mux + wire QZI = (QDS) ? QDI : CZI; + + // The flip-flop + initial QZ <= 1'b0; + always @(posedge QCK or posedge QST or posedge QRT) begin + if (QST) + QZ <= 1'b1; + else if (QRT) + QZ <= 1'b0; + else if (QEN) + QZ <= QZI; + end + + // =============== F_FRAG =============== + + input wire F1; + input wire F2; + input wire FS; + + (* DELAY_CONST_F1="1e-10" *) + (* DELAY_CONST_F2="1e-10" *) + (* DELAY_CONST_FS="1e-10" *) + output wire FZ; + + // The F-mux + assign FZ = FS ? F2 : F1; + +endmodule