docs: Rearrange layout - Rename docs/tests/ to docs/examples/ as it fits the content more closely - Add examples main page - Add description for clock examples page Signed-off-by: Daniel Lim Wee Soong <weesoong.lim@gmail.com>
diff --git a/README.md b/README.md index eceb48e..fee6994 100644 --- a/README.md +++ b/README.md
@@ -1,13 +1,14 @@ -# python-symbiflow-v2x +# SymbiFlow Verilog to XML [](https://python-symbiflow-v2x.readthedocs.io/en/latest/?badge=latest) [](https://travis-ci.com/SymbiFlow/python-symbiflow-v2x) -Tool for converting specialized annotated Verilog models into XML needed for +v2x is a tool for converting specialized annotated Verilog models into XML needed for [Verilog to Routing flow](https://docs.verilogtorouting.org/en/latest/arch/reference/). -Documentation can be found at https://python-symbiflow-v2x.readthedocs.io/en/latest/ +Documentation can be found at [https://python-symbiflow-v2x.readthedocs.io/en/latest/](https://python-symbiflow-v2x.readthedocs.io/en/latest/examples.html). ## Installation + v2x can be installed from a local git repository using pip. ``` @@ -18,7 +19,7 @@ Alternatively, it can be installed from GitHub directly. ``` -pip install git+https://github.com/SymbiFlow/python-symbiflow-v2x.git +pip install git+https://github.com/SymbiFlow/python-symbiflow-v2x.git#egg=python-symbiflow-v2x ``` ## Usage @@ -69,6 +70,7 @@ ``` ## Tests + The test cases are stored in tests/, and pytest can be used to run them. ``` @@ -84,6 +86,7 @@ ``` ## Documentation + We use sphinx for our documentation and the files are stored in docs/. To host it locally (if you are planning to update it), you can use the Makefile inside. First, run `make env` to prepare a Conda environment that contains the necessary packages to build and host the documentation site. After that, simply run `make livehtml` which starts a local server running at port 8000 with the documentation site. @@ -96,4 +99,7 @@ ## Talks -[](https://www.youtube.com/watch?v=a31vH_tZLBM) \ No newline at end of file +**VPR device models generation from Verilog with V2X - Karol Gugala - ORConf 2019** + +[](https://www.youtube.com/watch?v=a31vH_tZLBM) +
diff --git a/docs/examples.rst b/docs/examples.rst new file mode 100644 index 0000000..1978003 --- /dev/null +++ b/docs/examples.rst
@@ -0,0 +1,10 @@ +Examples +============ + +Here we have examples on how v2x converts a Verilog module to its corresponding model.xml and pb_type.xml files. These examples are taken from the `v2x test cases <https://github.com/SymbiFlow/python-symbiflow-v2x/tree/master/tests>`_. + +.. toctree:: + + examples/clocks.rst + examples/dsp.rst + examples/vtr-examples.rst \ No newline at end of file
diff --git a/docs/examples/clocks.rst b/docs/examples/clocks.rst new file mode 100644 index 0000000..c596af1 --- /dev/null +++ b/docs/examples/clocks.rst
@@ -0,0 +1,12 @@ +.. Clock Example Tests + +Clock +============== + +There are various ways for an input or output port to be detected as a clock by v2x. Here are examples on ways to do so. + +.. toctree:: + clocks/autodetection.rst + clocks/manual_input.rst + clocks/manual_output.rst + clocks/multiple.rst
diff --git a/docs/tests/clocks/autodetection.rst b/docs/examples/clocks/autodetection.rst similarity index 100% rename from docs/tests/clocks/autodetection.rst rename to docs/examples/clocks/autodetection.rst
diff --git a/docs/tests/clocks/manual_input.rst b/docs/examples/clocks/manual_input.rst similarity index 100% rename from docs/tests/clocks/manual_input.rst rename to docs/examples/clocks/manual_input.rst
diff --git a/docs/tests/clocks/manual_output.rst b/docs/examples/clocks/manual_output.rst similarity index 100% rename from docs/tests/clocks/manual_output.rst rename to docs/examples/clocks/manual_output.rst
diff --git a/docs/tests/clocks/multiple.rst b/docs/examples/clocks/multiple.rst similarity index 100% rename from docs/tests/clocks/multiple.rst rename to docs/examples/clocks/multiple.rst
diff --git a/docs/tests/dsp.rst b/docs/examples/dsp.rst similarity index 94% rename from docs/tests/dsp.rst rename to docs/examples/dsp.rst index 6fb30c7..7bc7e39 100644 --- a/docs/tests/dsp.rst +++ b/docs/examples/dsp.rst
@@ -1,6 +1,6 @@ .. DSP Based Example Tests -DSP Examples +DSP ============ .. toctree::
diff --git a/docs/tests/vtr-examples.rst b/docs/examples/vtr-examples.rst similarity index 89% rename from docs/tests/vtr-examples.rst rename to docs/examples/vtr-examples.rst index 33e94d9..98c0b22 100644 --- a/docs/tests/vtr-examples.rst +++ b/docs/examples/vtr-examples.rst
@@ -1,6 +1,6 @@ .. Examples from the Verilog to Routing documentation / tutorials. -Verilog to Routing Examples +Verilog to Routing =========================== Primitive Block Timing Modeling Tutorial
diff --git a/docs/index.rst b/docs/index.rst index d950667..6c144c0 100644 --- a/docs/index.rst +++ b/docs/index.rst
@@ -5,12 +5,4 @@ :glob: :hidden: - tests/vtr-examples.rst - tests/dsp.rst - -.. toctree:: - :maxdepth: 3 - :glob: - :hidden: - - tests/clocks.rst \ No newline at end of file + examples.rst
diff --git a/docs/tests/clocks.rst b/docs/tests/clocks.rst deleted file mode 100644 index bd33ad6..0000000 --- a/docs/tests/clocks.rst +++ /dev/null
@@ -1,10 +0,0 @@ -.. Clock Example Tests - -Clock Examples -============== - -.. toctree:: - clocks/autodetection.rst - clocks/manual_input.rst - clocks/manual_output.rst - clocks/multiple.rst