Added test-examples to verify CI Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/docs/examples/clocks.rst b/docs/examples/clocks.rst deleted file mode 100644 index fc6adc5..0000000 --- a/docs/examples/clocks.rst +++ /dev/null
@@ -1,12 +0,0 @@ -.. Clock Example Tests - -Clock -===== - -There are various ways for an input or output port to be detected as a clock by v2x. Here are examples on ways to do so. - -.. toctree:: - clocks/autodetection.rst - clocks/manual_input.rst - clocks/manual_output.rst - clocks/multiple.rst
diff --git a/docs/examples/clocks/autodetection.rst b/docs/examples/clocks/autodetection.rst deleted file mode 100644 index 789cf52..0000000 --- a/docs/examples/clocks/autodetection.rst +++ /dev/null
@@ -1,6 +0,0 @@ -Autodetection of clock from flipflop -==================================== - -.. include:: ../../../tests/clocks/dff_one_clock/README.rst -.. include:: ../../../tests/clocks/dff_comb_one_clock/README.rst -.. include:: ../../../tests/clocks/dff_two_clocks/README.rst
diff --git a/docs/examples/clocks/manual_input.rst b/docs/examples/clocks/manual_input.rst deleted file mode 100644 index a5d6b39..0000000 --- a/docs/examples/clocks/manual_input.rst +++ /dev/null
@@ -1,7 +0,0 @@ -Manually set inputs as clock -============================ - -.. include:: ../../../tests/clocks/input_attr_clock/README.rst -.. include:: ../../../tests/clocks/input_attr_not_clock/README.rst -.. include:: ../../../tests/clocks/input_named_clk/README.rst -.. include:: ../../../tests/clocks/input_named_regex/README.rst
diff --git a/docs/examples/clocks/manual_output.rst b/docs/examples/clocks/manual_output.rst deleted file mode 100644 index 39e7894..0000000 --- a/docs/examples/clocks/manual_output.rst +++ /dev/null
@@ -1,5 +0,0 @@ -Manually set outputs as clock -============================= - -.. include:: ../../../tests/clocks/output_attr_clock/README.rst -.. include:: ../../../tests/clocks/output_named_clk/README.rst
diff --git a/docs/examples/clocks/multiple.rst b/docs/examples/clocks/multiple.rst deleted file mode 100644 index 596ad4b..0000000 --- a/docs/examples/clocks/multiple.rst +++ /dev/null
@@ -1,5 +0,0 @@ -Multiple clocks -=============== - -.. include:: ../../../tests/clocks/multiple_inputs_named_clk/README.rst -.. include:: ../../../tests/clocks/multiple_outputs_named_clk/README.rst
diff --git a/docs/examples/dsp.rst b/docs/examples/dsp.rst deleted file mode 100644 index 0b043e8..0000000 --- a/docs/examples/dsp.rst +++ /dev/null
@@ -1,20 +0,0 @@ -DSP -=== - -.. some aliases for the included rst files to use - -.. |fig60| replace:: ``Figure 60 - DFF`` -.. _fig60: /examples/vtr/primitive.html#classical-d-flip-flop-test - -.. |dsp_combinational| replace:: ``dsp_combinational`` -.. _dsp_combinational: #combinational-dsp - -The following shows some DSP-based examples. - -.. include:: ../../tests/dsp/dsp_combinational/README.rst -.. include:: ../../tests/dsp/dsp_partial_registered/README.rst -.. include:: ../../tests/dsp/dsp_in_registered/README.rst -.. include:: ../../tests/dsp/dsp_out_registered/README.rst -.. include:: ../../tests/dsp/dsp_inout_registered/README.rst -.. include:: ../../tests/dsp/dsp_inout_registered_dualclk/README.rst -.. include:: ../../tests/dsp/dsp_modes/README.rst
diff --git a/docs/examples/vtr-examples.rst b/docs/examples/vtr-examples.rst deleted file mode 100644 index c3c87f9..0000000 --- a/docs/examples/vtr-examples.rst +++ /dev/null
@@ -1,10 +0,0 @@ -.. Examples from the Verilog to Routing documentation / tutorials. - -Verilog to Routing -================== - -The following shows some examples taken from the `Verilog to Routing documentation <https://docs.verilogtorouting.org>`_. - -.. toctree:: - vtr/primitive.rst - vtr/arch.rst \ No newline at end of file
diff --git a/docs/examples/vtr/arch.rst b/docs/examples/vtr/arch.rst deleted file mode 100644 index 750ee16..0000000 --- a/docs/examples/vtr/arch.rst +++ /dev/null
@@ -1,8 +0,0 @@ -Architecture Reference -====================== - -The following shows examples taken from the -`Architecture Reference section <https://docs.verilogtorouting.org/en/latest/arch/reference>`_ -in the `Verilog to Routing documentation <https://docs.verilogtorouting.org>`_. - -.. include:: ../../../tests/vtr/lutff-pair/README.rst \ No newline at end of file
diff --git a/docs/examples/vtr/primitive.rst b/docs/examples/vtr/primitive.rst deleted file mode 100644 index 0aa5545..0000000 --- a/docs/examples/vtr/primitive.rst +++ /dev/null
@@ -1,9 +0,0 @@ -Primitive Block Timing Modeling Tutorial -======================================== - -The following shows examples taken from the -`Primitive Block Timing Modeling Tutorial <https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#>`_ -in the `Verilog to Routing documentation <https://docs.verilogtorouting.org>`_. - -.. include:: ../../../tests/vtr/dff/README.rst -.. include:: ../../../tests/vtr/full-adder/README.rst \ No newline at end of file
diff --git a/tests/gates/README.rst b/tests/gates/README.rst new file mode 100644 index 0000000..85c8997 --- /dev/null +++ b/tests/gates/README.rst
@@ -0,0 +1,12 @@ +.. Gates + +These are some gates +==================== + +The following shows some examples taken from the tests + +.. toctree:: + not/README.rst + and/README.rst + nor/README.rst + xor/README.rst
diff --git a/tests/gates/and/README.rst b/tests/gates/and/README.rst new file mode 100644 index 0000000..9cce6a2 --- /dev/null +++ b/tests/gates/and/README.rst
@@ -0,0 +1,28 @@ +AND gate +======== + +This is an AND gate + +.. symbolator:: and.sim.v + +.. verilog-diagram:: and.sim.v + :type: netlistsvg + :module: AND + +| + +.. no-license:: and.sim.v + :language: verilog + :caption: and.sim.v + +The gate model generated by V2X + +.. literalinclude:: and.model.xml + :language: xml + :caption: and.model.xml + +The gate pb_type generated by V2X + +.. literalinclude:: and.pb_type.xml + :language: xml + :caption: and.pb_type.xml
diff --git a/tests/gates/and/and.sim.v b/tests/gates/and/and.sim.v new file mode 100644 index 0000000..be2ee47 --- /dev/null +++ b/tests/gates/and/and.sim.v
@@ -0,0 +1,19 @@ +/* + * Copyright (C) 2020 The SymbiFlow Authors. + * + * Use of this source code is governed by a ISC-style + * license that can be found in the LICENSE file or at + * https://opensource.org/licenses/ISC + * + * SPDX-License-Identifier: ISC + */ + +module AND ( + input A, + input B, + output Y +); + + assign Y = A & B; + +endmodule
diff --git a/tests/gates/and/golden.model.xml b/tests/gates/and/golden.model.xml new file mode 100644 index 0000000..497ac6a --- /dev/null +++ b/tests/gates/and/golden.model.xml
@@ -0,0 +1,11 @@ +<models xmlns:xi="http://www.w3.org/2001/XInclude"> + <model name="AND"> + <input_ports> + <port name="A" combinational_sink_ports="Y"/> + <port name="B" combinational_sink_ports="Y"/> + </input_ports> + <output_ports> + <port name="Y"/> + </output_ports> + </model> +</models>
diff --git a/tests/gates/and/golden.pb_type.xml b/tests/gates/and/golden.pb_type.xml new file mode 100644 index 0000000..23ee9ee --- /dev/null +++ b/tests/gates/and/golden.pb_type.xml
@@ -0,0 +1,7 @@ +<?xml version='1.0' encoding='utf-8'?> +<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" num_pb="1" name="AND"> + <blif_model>.subckt AND</blif_model> + <input name="A" num_pins="1"/> + <input name="B" num_pins="1"/> + <output name="Y" num_pins="1"/> +</pb_type>
diff --git a/tests/gates/nor/README.rst b/tests/gates/nor/README.rst new file mode 100644 index 0000000..a28ada0 --- /dev/null +++ b/tests/gates/nor/README.rst
@@ -0,0 +1,28 @@ +NOR gate +======== + +This is an NOR gate + +.. symbolator:: nor.sim.v + +.. verilog-diagram:: nor.sim.v + :type: netlistsvg + :module: NOR + +| + +.. no-license:: nor.sim.v + :language: verilog + :caption: nor.sim.v + +The gate model generated by V2X + +.. literalinclude:: nor.model.xml + :language: xml + :caption: nor.model.xml + +The gate pb_type generated by V2X + +.. literalinclude:: nor.pb_type.xml + :language: xml + :caption: nor.pb_type.xml
diff --git a/tests/gates/nor/golden.model.xml b/tests/gates/nor/golden.model.xml new file mode 100644 index 0000000..d4900dd --- /dev/null +++ b/tests/gates/nor/golden.model.xml
@@ -0,0 +1,11 @@ +<models xmlns:xi="http://www.w3.org/2001/XInclude"> + <model name="NOR"> + <input_ports> + <port name="A" combinational_sink_ports="Y"/> + <port name="B" combinational_sink_ports="Y"/> + </input_ports> + <output_ports> + <port name="Y"/> + </output_ports> + </model> +</models>
diff --git a/tests/gates/nor/golden.pb_type.xml b/tests/gates/nor/golden.pb_type.xml new file mode 100644 index 0000000..d533ac5 --- /dev/null +++ b/tests/gates/nor/golden.pb_type.xml
@@ -0,0 +1,7 @@ +<?xml version='1.0' encoding='utf-8'?> +<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" num_pb="1" name="NOR"> + <blif_model>.subckt NOR</blif_model> + <input name="A" num_pins="1"/> + <input name="B" num_pins="1"/> + <output name="Y" num_pins="1"/> +</pb_type>
diff --git a/tests/gates/nor/nor.sim.v b/tests/gates/nor/nor.sim.v new file mode 100644 index 0000000..7517e0e --- /dev/null +++ b/tests/gates/nor/nor.sim.v
@@ -0,0 +1,19 @@ +/* + * Copyright (C) 2020 The SymbiFlow Authors. + * + * Use of this source code is governed by a ISC-style + * license that can be found in the LICENSE file or at + * https://opensource.org/licenses/ISC + * + * SPDX-License-Identifier: ISC + */ + +module NOR ( + input A, + input B, + output Y +); + + assign Y = ~(A | B); + +endmodule
diff --git a/tests/gates/not/README.rst b/tests/gates/not/README.rst new file mode 100644 index 0000000..5ba2b65 --- /dev/null +++ b/tests/gates/not/README.rst
@@ -0,0 +1,28 @@ +NOT gate +======== + +This is an NOT gate + +.. symbolator:: not.sim.v + +.. verilog-diagram:: not.sim.v + :type: netlistsvg + :module: NOT + +| + +.. no-license:: not.sim.v + :language: verilog + :caption: not.sim.v + +The gate model generated by V2X + +.. literalinclude:: not.model.xml + :language: xml + :caption: not.model.xml + +The gate pb_type generated by V2X + +.. literalinclude:: not.pb_type.xml + :language: xml + :caption: not.pb_type.xml
diff --git a/tests/gates/not/golden.model.xml b/tests/gates/not/golden.model.xml new file mode 100644 index 0000000..a9badad --- /dev/null +++ b/tests/gates/not/golden.model.xml
@@ -0,0 +1,10 @@ +<models xmlns:xi="http://www.w3.org/2001/XInclude"> + <model name="NOT"> + <input_ports> + <port name="A" combinational_sink_ports="Y"/> + </input_ports> + <output_ports> + <port name="Y"/> + </output_ports> + </model> +</models>
diff --git a/tests/gates/not/golden.pb_type.xml b/tests/gates/not/golden.pb_type.xml new file mode 100644 index 0000000..864b55f --- /dev/null +++ b/tests/gates/not/golden.pb_type.xml
@@ -0,0 +1,6 @@ +<?xml version='1.0' encoding='utf-8'?> +<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" num_pb="1" name="NOT"> + <blif_model>.subckt NOT</blif_model> + <input name="A" num_pins="1"/> + <output name="Y" num_pins="1"/> +</pb_type>
diff --git a/tests/gates/not/not.sim.v b/tests/gates/not/not.sim.v new file mode 100644 index 0000000..0452fd2 --- /dev/null +++ b/tests/gates/not/not.sim.v
@@ -0,0 +1,18 @@ +/* + * Copyright (C) 2020 The SymbiFlow Authors. + * + * Use of this source code is governed by a ISC-style + * license that can be found in the LICENSE file or at + * https://opensource.org/licenses/ISC + * + * SPDX-License-Identifier: ISC + */ + +module NOT ( + input A, + output Y +); + + assign Y = ~A; + +endmodule
diff --git a/tests/gates/xor/README.rst b/tests/gates/xor/README.rst new file mode 100644 index 0000000..1c13dd7 --- /dev/null +++ b/tests/gates/xor/README.rst
@@ -0,0 +1,28 @@ +XOR gate +======== + +This is a XOR gate made of NOR gates + +.. symbolator:: xor.sim.v + +.. verilog-diagram:: xor.sim.v + :type: netlistsvg + :module: XOR + +| + +.. no-license:: xor.sim.v + :language: verilog + :caption: xor.sim.v + +The gate model generated by V2X + +.. literalinclude:: xor.model.xml + :language: xml + :caption: xor.model.xml + +The gate pb_type generated by V2X + +.. literalinclude:: xor.pb_type.xml + :language: xml + :caption: xor.pb_type.xml
diff --git a/tests/gates/xor/golden.model.xml b/tests/gates/xor/golden.model.xml new file mode 100644 index 0000000..990bc88 --- /dev/null +++ b/tests/gates/xor/golden.model.xml
@@ -0,0 +1,3 @@ +<models xmlns:xi="http://www.w3.org/2001/XInclude"> + <xi:include href="../nor/nor.model.xml" xpointer="xpointer(models/child::node())"/> +</models>
diff --git a/tests/gates/xor/golden.pb_type.xml b/tests/gates/xor/golden.pb_type.xml new file mode 100644 index 0000000..7ea5823 --- /dev/null +++ b/tests/gates/xor/golden.pb_type.xml
@@ -0,0 +1,72 @@ +<?xml version='1.0' encoding='utf-8'?> +<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" num_pb="1" name="XOR"> + <input name="A" num_pins="1"/> + <input name="B" num_pins="1"/> + <output name="Y" num_pins="1"/> + <pb_type num_pb="1" name="nor00"> + <!--old_name NOR--> + <xi:include href="../nor/nor.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/> + </pb_type> + <pb_type num_pb="1" name="nor10"> + <!--old_name NOR--> + <xi:include href="../nor/nor.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/> + </pb_type> + <pb_type num_pb="1" name="nor11"> + <!--old_name NOR--> + <xi:include href="../nor/nor.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/> + </pb_type> + <pb_type num_pb="1" name="nor20"> + <!--old_name NOR--> + <xi:include href="../nor/nor.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/> + </pb_type> + <pb_type num_pb="1" name="nor30"> + <!--old_name NOR--> + <xi:include href="../nor/nor.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/> + </pb_type> + <interconnect> + <direct> + <port name="A" type="input"/> + <port name="A" type="output" from="nor00"/> + </direct> + <direct> + <port name="A" type="input"/> + <port name="A" type="output" from="nor10"/> + </direct> + <direct> + <port name="B" type="input"/> + <port name="B" type="output" from="nor00"/> + </direct> + <direct> + <port name="B" type="input"/> + <port name="A" type="output" from="nor11"/> + </direct> + <direct> + <port name="Y" type="input" from="nor00"/> + <port name="B" type="output" from="nor10"/> + </direct> + <direct> + <port name="Y" type="input" from="nor00"/> + <port name="B" type="output" from="nor11"/> + </direct> + <direct> + <port name="Y" type="input" from="nor10"/> + <port name="A" type="output" from="nor20"/> + </direct> + <direct> + <port name="Y" type="input" from="nor11"/> + <port name="B" type="output" from="nor20"/> + </direct> + <direct> + <port name="Y" type="input" from="nor20"/> + <port name="A" type="output" from="nor30"/> + </direct> + <direct> + <port name="Y" type="input" from="nor20"/> + <port name="B" type="output" from="nor30"/> + </direct> + <direct> + <port name="Y" type="input" from="nor30"/> + <port name="Y" type="output"/> + </direct> + </interconnect> +</pb_type>
diff --git a/tests/gates/xor/xor.sim.v b/tests/gates/xor/xor.sim.v new file mode 100644 index 0000000..23adbb4 --- /dev/null +++ b/tests/gates/xor/xor.sim.v
@@ -0,0 +1,32 @@ +/* + * Copyright (C) 2020 The SymbiFlow Authors. + * + * Use of this source code is governed by a ISC-style + * license that can be found in the LICENSE file or at + * https://opensource.org/licenses/ISC + * + * SPDX-License-Identifier: ISC + */ + +`include "../nor/nor.sim.v" + +module XOR ( + input A, + input B, + output Y +); + + wire S00; + NOR nor00 (.A(A), .B(B), .Y(S00)); + + wire S10; + wire S11; + NOR nor10 (.A(A), .B(S00), .Y(S10)); + NOR nor11 (.A(B), .B(S00), .Y(S11)); + + wire S20; + NOR nor20 (.A(S10), .B(S11), .Y(S20)); + + NOR nor30 (.A(S20), .B(S20), .Y(Y)); + +endmodule
diff --git a/tests/internal_conn/README.rst b/tests/internal_conn/README.rst.bak similarity index 100% rename from tests/internal_conn/README.rst rename to tests/internal_conn/README.rst.bak
diff --git a/tests/io/README.rst b/tests/io/README.rst.bak similarity index 100% rename from tests/io/README.rst rename to tests/io/README.rst.bak
diff --git a/tests/net_attr/README.rst b/tests/net_attr/README.rst.bak similarity index 100% rename from tests/net_attr/README.rst rename to tests/net_attr/README.rst.bak
diff --git a/tests/no_comb/README.rst b/tests/no_comb/README.rst.bak similarity index 100% rename from tests/no_comb/README.rst rename to tests/no_comb/README.rst.bak