Fix formatting accorgding to flake8 Signed-off-by: Karol Gugala <kgugala@antmicro.com>
diff --git a/setup.py b/setup.py index 14b64ef..f88cf63 100644 --- a/setup.py +++ b/setup.py
@@ -22,7 +22,4 @@ "License :: OSI Approved :: ISC License", "Operating System :: OS Independent", ], - #entry_points={ - # 'console_scripts': ['sdf_timing_parse=sdf_timing.sdfparse:main'], - #}, )
diff --git a/v2x/__main__.py b/v2x/__main__.py index 91cd92d..8ab0174 100644 --- a/v2x/__main__.py +++ b/v2x/__main__.py
@@ -5,13 +5,17 @@ import argparse import sys + def main(args): if args.mode == "pb_type": with open(args.outfile, "w") as fp: - fp.write(vlog_to_pbtype.vlog_to_pbtype(args.infiles, args.outfile, args.top)) + fp.write(vlog_to_pbtype.vlog_to_pbtype( + args.infiles, args.outfile, args.top)) else: with open(args.outfile, "w") as fp: - fp.write(vlog_to_model.vlog_to_model(args.infiles, args.includes, args.top, args.outfile)) + fp.write(vlog_to_model.vlog_to_model( + args.infiles, args.includes, args.top, args.outfile)) + if __name__ == '__main__': parser = argparse.ArgumentParser(
diff --git a/v2x/vlog_to_model.py b/v2x/vlog_to_model.py index f95d924..6e6fca8 100755 --- a/v2x/vlog_to_model.py +++ b/v2x/vlog_to_model.py
@@ -5,18 +5,19 @@ The following Verilog attributes are considered on ports: - `(* CLOCK *)` : force a given port to be a clock - - `(* ASSOC_CLOCK="RDCLK" *)` : force a port's associated clock to a given value + - `(* ASSOC_CLOCK="RDCLK" *)` : force a port's associated + clock to a given value The following Verilog attributes are considered on modules: - - `(* MODEL_NAME="model" *)` : override the name used for <model> and for - ".subckt name" in the BLIF model. Mostly intended for use with w.py, when several - different pb_types implement the same model. + - `(* MODEL_NAME="model" *)` : override the name used for + <model> and for ".subckt name" in the BLIF model. Mostly + intended for use with w.py, when several different pb_types + implement the same model. - - `(* CLASS="lut|routing|mux|flipflop|mem" *)` : specify the class of an given - instance. A model will not be generated for the `lut`, `routing` or `flipflop` - class. + - `(* CLASS="lut|routing|mux|flipflop|mem" *)` : specify the + class of an given instance. A model will not be generated for + the `lut`, `routing` or `flipflop` class. """ -import argparse import os import re import sys @@ -74,6 +75,7 @@ return False + def vlog_to_model(infiles, includes, top, outfile=None): iname = os.path.basename(infiles[0]) @@ -143,7 +145,8 @@ wm.group(1).lower() ) else: - assert False, "included Verilog file name {} does not follow pattern %%.sim.v".format( + assert False, "included Verilog file name {} does \ + not follow pattern %%.sim.v".format( module_basename ) xmlinc.include_xml( @@ -177,8 +180,8 @@ if is_registered_path(tmod, name, sink): sinks.remove(sink) - # FIXME: Check if ignoring clock for "combination_sink_ports" is a - # valid thing to do. + # FIXME: Check if ignoring clock for "combination_sink_ports" + # is a valid thing to do. if name in clocks or "clk" in name.lower(): attrs["is_clock"] = "1" else: @@ -195,10 +198,11 @@ elif iodir == "output": ET.SubElement(outports_xml, "port", attrs) else: - assert False, "bidirectional ports not permitted in VPR models" + assert False, "bidirectional ports not permitted \ + in VPR models" if len(models_xml) == 0: - models_xml.insert(0, ET.Comment("this file is intentionally left blank")) + models_xml.insert(0, + ET.Comment("this file is intentionally left blank")) return ET.tostring(models_xml, pretty_print=True).decode('utf-8') -
diff --git a/v2x/vlog_to_pbtype.py b/v2x/vlog_to_pbtype.py index 6333de6..f88a43c 100755 --- a/v2x/vlog_to_pbtype.py +++ b/v2x/vlog_to_pbtype.py
@@ -9,49 +9,56 @@ This will also set the BLIF model to be `.subckt <name>` unless CLASS is also specified. - - `(* CLASS="lut|routing|mux|flipflop|mem" *)` : specify the class of an given - instance. + - `(* CLASS="lut|routing|mux|flipflop|mem" *)` : specify the class of an + given instance. - - `(* MODES="mode1; mode2; ..." *)` : specify that the module has more than one functional - mode, each with a given name. The module will be evaluated n times, each time setting - the MODE parameter to the nth value in the list of mode names. Each evaluation will be - put in a pb_type `<mode>` section named accordingly. + - `(* MODES="mode1; mode2; ..." *)` : specify that the module has more + than one functional mode, each with a given name. The module will be + evaluated n times, each time setting the MODE parameter to the nth value + in the list of mode names. Each evaluation will be put in a pb_type + `<mode>` section named accordingly. - `(* MODEL_NAME="model" *)` : override the name used for <model> and for - ".subckt name" in the BLIF model. Mostly intended for use with w.py, when several - different pb_types implement the same model. + ".subckt name" in the BLIF model. Mostly intended for use with w.py, when + several different pb_types implement the same model. -The following are allowed on nets within modules (TODO: use proper Verilog timing): +The following are allowed on nets within modules +(TODO: use proper Verilog timing): - `(* SETUP="clk 10e-12" *)` : specify setup time for a given clock - `(* HOLD="clk 10e-12" *)` : specify hold time for a given clock - - `(* CLK_TO_Q="clk 10e-12" *)` : specify clock-to-output time for a given clock + - `(* CLK_TO_Q="clk 10e-12" *)` : specify clock-to-output time for + a given clock - - `(* DELAY_CONST_{input}="30e-12" *)` : specify a constant max delay from an input - (applied to the output) + - `(* DELAY_CONST_{input}="30e-12" *)` : specify a constant max delay + from an input (applied to the + output) - - `(* DELAY_MATRIX_{input}="30e-12 35e-12; 20e-12 25e-12; ..." *)` : specify a VPR - delay matrix (semicolons indicate rows). In this format columns specify - inputs bits and rows specify output bits. This should be applied to the output. + - `(* DELAY_MATRIX_{input}="30e-12 35e-12; 20e-12 25e-12; ..." *)` : + specify a VPR delay matrix (semicolons indicate rows). In this + format columns specify inputs bits and rows specify output bits. + This should be applied to the output. - - `(* carry = ADDER *)` : specify carry chain pack_pattern associated with this wire + - `(* carry = ADDER *)` : specify carry chain pack_pattern associated + with this wire The following are allowed on ports: - `(* CLOCK *)` : force a given port to be a clock - - `(* ASSOC_CLOCK="RDCLK" *)` : force a port's associated clock to a given value + - `(* ASSOC_CLOCK="RDCLK" *)` : force a port's associated clock to a + given value - `(* PORT_CLASS="clock" *)` : specify the VPR "port_class" - - `(* carry = ADDER *)` : specify carry chain pack_pattern associated with this port + - `(* carry = ADDER *)` : specify carry chain pack_pattern associated + with this port The Verilog define "PB_TYPE" is set during generation. """ import os import sys -import argparse import re from typing import List, Dict, Tuple @@ -111,12 +118,12 @@ def strip_name(name: str, include_index=True) -> str: """Convert generate block into normal array form. - >>> n = r"$genblock$/vlog/tests/multiple_instance/multiple_instance.sim.v:12$64[57].\\comb" + >>> n = r"$genblock$/tests/multiple_instance/multiple_instance.sim.v:12$64[57].\\comb" # noqa: E501 >>> strip_name(n) 'comb[57]' >>> strip_name(n, False) 'comb' - >>> n = r"$genblock$/vlog/tests/multiple_instance/multiple_instance.sim.v:15$10[3].\\comba" + >>> n = r"$genblock$/tests/multiple_instance/multiple_instance.sim.v:15$10[3].\\comba" # noqa: #501 >>> strip_name(n) 'comba[3]' """ @@ -287,11 +294,13 @@ for pin, net in inp_cons: drvs = mod.net_drivers(net) assert len(drvs) > 0, ( - "ERROR: pin {}.{} has no driver, interconnect will be missing\n{}" + "ERROR: pin {}.{} has no driver, \ + interconnect will be missing\n{}" .format(cname, pin, mod) ) assert len(drvs) < 2, ( - "ERROR: pin {}.{} has multiple drivers, interconnect will be overspecified" + "ERROR: pin {}.{} has multiple drivers, \ + interconnect will be overspecified" .format(cname, pin) ) for drv_cell, drv_pin in drvs: @@ -365,7 +374,8 @@ assert d[cname_prefix][ 0 ] == ctype, \ - "Type of {} with prefix {} doesn't match existing. Type: {}, existing: {}".format( + "Type of {} with prefix {} doesn't match \ + existing. Type: {}, existing: {}".format( cname, cname_prefix, ctype, children[cname_prefix] ) d[cname_prefix][-1].append(strip_name(cname)) @@ -603,7 +613,8 @@ driver_cell, driver_pin, mux_cell, sink_pin ) assert sink_pin not in mux_inputs, """\ -Pin {}.{} is trying to drive mux pin {}.{} (already driving by {}.{})""".format( +Pin {}.{} is trying to drive mux pin {}.{} (already driving by {}.{})\ + """.format( driver_cell, driver_pin, mux_cell, mux_pin, *mux_inputs[sink_pin] ) @@ -620,14 +631,15 @@ splitspec = tmgspec.split(" ") assert len( splitspec - ) == 2, 'bad timing specification "{}", must be of format "clock value"'.format( - tmgspec - ) + ) == 2, 'bad timing specification "{}", must be of format \ + "clock value"'.format(tmgspec) + attrs = {"port": port, "clock": splitspec[0]} if xmltype == "T_clock_to_Q": assert iodir == "output", \ - "Only output ports can have T_clock_to_Q timing definition." - "Port {}, direction {}.".format(port, iodir) + "Only output ports can have T_clock_to_Q timing \ + definition. Port {}, direction {}.".format( + port, iodir) attrs["max"] = splitspec[1] else: assert iodir == "input", \ @@ -677,7 +689,8 @@ def make_pb_type( - infiles, outfile, yj, mod, mode_processing=False, mode_xml=None, mode_name=None + infiles, outfile, yj, mod, mode_processing=False, + mode_xml=None, mode_name=None ): """Build the pb_type for a given module. mod is the YosysModule object to generate.""" @@ -767,9 +780,11 @@ ) ) mode_mod = mode_yj.module(mod.name) - make_pb_type(infiles, outfile, mode_yj, mode_mod, True, mode_xml, smode) + make_pb_type(infiles, outfile, mode_yj, mode_mod, + True, mode_xml, smode) - # if mode pb_type contains interconnect tag, add new connctions there + # if mode pb_type contains interconnect tag, + # add new connctions there ic_xml = mode_xml.find("interconnect") print("ic_xml is", ic_xml, file=sys.stderr) if ic_xml is None: @@ -797,6 +812,7 @@ return pb_type_xml + def vlog_to_pbtype(infiles, outfile, top=None): iname = os.path.basename(infiles[0]) @@ -812,8 +828,9 @@ top = wm.group(1).upper() else: print( - "ERROR file name not of format %.sim.v ({}), cannot detect top level." - " Manually specify the top level module using --top". + "ERROR file name not of format %.sim.v ({})," + " cannot detect top level. Manually specify" + " the top level module using --top". format(iname) ) sys.exit(1) @@ -830,4 +847,3 @@ encoding="utf-8", xml_declaration=True ).decode('utf-8') -
diff --git a/v2x/yosys/json.py b/v2x/yosys/json.py index d743127..7278773 100755 --- a/v2x/yosys/json.py +++ b/v2x/yosys/json.py
@@ -125,7 +125,8 @@ return self.data["netnames"][netname]["attributes"] def net_attr(self, netname, attr, defval=None): - """Get an attribute of a given net (specified by name), or defval is not set""" + """Get an attribute of a given net (specified by name), + or defval is not set""" if attr in self.net_attrs(netname): return self.net_attrs(netname)[attr] else: @@ -336,7 +337,8 @@ return YosysModule(module, self.data["modules"][module]) def modules_with_attr(self, attr_name, attr_value): - """Return a list of `YosysModule`s, selecting based on a given attribute""" + """Return a list of `YosysModule`s, selecting based on + a given attribute""" mods = [] for mod in self.data["modules"]: ymod = self.module(mod) @@ -345,7 +347,8 @@ return mods def all_modules(self): - """Return a list of the names of all modules in the design, sorted alphabetically""" + """Return a list of the names of all modules in the design, + sorted alphabetically""" return sorted(self.data["modules"].keys()) @property
diff --git a/v2x/yosys/run.py b/v2x/yosys/run.py index 842f7e9..9b30c79 100755 --- a/v2x/yosys/run.py +++ b/v2x/yosys/run.py
@@ -29,7 +29,8 @@ def get_output(params): - """Run Yosys with given command line parameters, and return stdout as a string""" + """Run Yosys with given command line parameters, and return + stdout as a string""" verbose = get_verbose() @@ -76,19 +77,20 @@ def get_defines(): - """Return a list of set Verilog defines, as a list of arguments to pass to Yosys -`read_verilog`""" + """Return a list of set Verilog defines, as a list of arguments + to pass to Yosys `read_verilog`""" return " ".join(["-D" + _ for _ in defines]) def add_include(path): - """ Add a path to search when reading verilog to the list of includes set in Yosys""" + """ Add a path to search when reading verilog to the list of + includes set in Yosys""" includes.append(path) def get_includes(): - """Return a list of include directories, as a list of arguments to pass to Yosys -`read_verilog`""" + """Return a list of include directories, as a list of arguments + to pass to Yosys `read_verilog`""" return " ".join(["-I" + _ for _ in includes]) @@ -130,7 +132,8 @@ infiles : list of input files flatten : set to flatten output hierarchy aig : generate And-Inverter-Graph modules for gates - mode : set to a value other than None to use `chparam` to set the value of the MODE parameter + mode : set to a value other than None to use `chparam` to + set the value of the MODE parameter module_with_mode : the name of the module to apply `mode` to """ prep_opts = "-flatten" if flatten else "" @@ -166,8 +169,8 @@ def do_select(infiles, module, expr, prep=False, flatten=False): """ - Run a Yosys select command (given the expression and input files) on a module - and return the result as a list of pins + Run a Yosys select command (given the expression and input files) + on a module and return the result as a list of pins Inputs -------