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foss-fpga-tools/python-symbiflow-v2x/531dc8123d32ab83e013220f5056a91047224243^!/.
commit
531dc8123d32ab83e013220f5056a91047224243
[log]
author
Daniel Lim Wee Soong <weesoong.lim@gmail.com>
Thu Apr 16 18:59:21 2020 +0800
committer
Daniel Lim Wee Soong <weesoong.lim@gmail.com>
Mon Apr 27 11:05:51 2020 +0800
tree
c2c186110a96853b22a6ab0919d0f1841d65b827
parent
9e518ea9a3eb18c002187e9089e3bd4cbb5fbaa5 [diff]
Add verilog-diagram to the examples

Signed-off-by: Daniel Lim Wee Soong <weesoong.lim@gmail.com>

diff --git a/tests/clocks/dff_comb_one_clock/README.rst b/tests/clocks/dff_comb_one_clock/README.rst
index 8661b73..7fb837d 100644
--- a/tests/clocks/dff_comb_one_clock/README.rst
+++ b/tests/clocks/dff_comb_one_clock/README.rst

@@ -5,6 +5,11 @@
 
 .. symbolator:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
 
+.. verilog-diagram:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
+   :type: netlistsvg
+   :module: BLOCK
+   :caption: tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
+
 .. literalinclude:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
    :language: verilog
 

diff --git a/tests/clocks/dff_one_clock/README.rst b/tests/clocks/dff_one_clock/README.rst
index fabe944..a92197b 100644
--- a/tests/clocks/dff_one_clock/README.rst
+++ b/tests/clocks/dff_one_clock/README.rst

@@ -5,6 +5,11 @@
 
 .. symbolator:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v
 
+.. verilog-diagram:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v
+   :type: netlistsvg
+   :module: BLOCK
+   :caption: tests/clocks/dff_one_clock/dff_one_clock.sim.v
+
 .. literalinclude:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v
    :language: verilog
 

diff --git a/tests/clocks/dff_two_clocks/README.rst b/tests/clocks/dff_two_clocks/README.rst
index c31723e..467cedf 100644
--- a/tests/clocks/dff_two_clocks/README.rst
+++ b/tests/clocks/dff_two_clocks/README.rst

@@ -5,6 +5,11 @@
 
 .. symbolator:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v
 
+.. verilog-diagram:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v
+   :type: netlistsvg
+   :module: BLOCK
+   :caption: tests/clocks/dff_two_clocks/dff_two_clocks.sim.v
+
 .. literalinclude:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v
    :language: verilog
 

diff --git a/tests/clocks/input_attr_clock/README.rst b/tests/clocks/input_attr_clock/README.rst
index dd48e6a..1f5b031 100644
--- a/tests/clocks/input_attr_clock/README.rst
+++ b/tests/clocks/input_attr_clock/README.rst

@@ -5,6 +5,11 @@
 
 .. symbolator:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v
 
+.. verilog-diagram:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v
+   :type: netlistsvg
+   :module: BLOCK
+   :caption: tests/clocks/input_attr_clock/input_attr_clock.sim.v
+
 .. literalinclude:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v
    :language: verilog
 

diff --git a/tests/clocks/input_attr_not_clock/README.rst b/tests/clocks/input_attr_not_clock/README.rst
index 22180a1..f51f554 100644
--- a/tests/clocks/input_attr_not_clock/README.rst
+++ b/tests/clocks/input_attr_not_clock/README.rst

@@ -3,9 +3,14 @@
 
 `input wire a` should be detected as a clock because it drives the flip flop. However, it has the attribute CLOCK set to 0 which should force it to be a regular input.
 
-.. symbolator:: ../../../tests/clocks/input_attr_not_clock/input_attr_not_clock.sim.v
+.. symbolator:: ../../../tests/clocks/input_attr_not_clock/block.sim.v
 
-.. literalinclude:: ../../../tests/clocks/input_attr_not_clock/input_attr_not_clock.sim.v
+.. verilog-diagram:: ../../../tests/clocks/input_attr_not_clock/block.sim.v
+   :type: netlistsvg
+   :module: BLOCK
+   :caption: tests/clocks/input_attr_not_clock/block.sim.v
+
+.. literalinclude:: ../../../tests/clocks/input_attr_not_clock/block.sim.v
    :language: verilog
 
 As such, the `is_clock` attribute of the `a` port is not set.

diff --git a/tests/clocks/input_attr_not_clock/input_attr_not_clock.sim.v b/tests/clocks/input_attr_not_clock/block.sim.v
similarity index 93%
rename from tests/clocks/input_attr_not_clock/input_attr_not_clock.sim.v
rename to tests/clocks/input_attr_not_clock/block.sim.v
index a2f8b11..856cdd0 100644
--- a/tests/clocks/input_attr_not_clock/input_attr_not_clock.sim.v
+++ b/tests/clocks/input_attr_not_clock/block.sim.v

@@ -13,7 +13,7 @@
  * flop. However, it has the attribute CLOCK set to 0 which should force it
  * to be a regular input.
  */
-module INPUT_ATTR_NOT_CLOCK(a, b, c);
+module BLOCK(a, b, c);
     (* CLOCK=0 *)
     input wire a;
     input wire b;

diff --git a/tests/clocks/input_attr_not_clock/golden.model.xml b/tests/clocks/input_attr_not_clock/golden.model.xml
index 56d6286..51ff8df 100644
--- a/tests/clocks/input_attr_not_clock/golden.model.xml
+++ b/tests/clocks/input_attr_not_clock/golden.model.xml

@@ -1,5 +1,5 @@
 <models xmlns:xi="http://www.w3.org/2001/XInclude">
-  <model name="INPUT_ATTR_NOT_CLOCK">
+  <model name="BLOCK">
     <input_ports>
       <port clock="a" combinational_sink_ports="c" name="a"/>
       <port clock="a" name="b"/>

diff --git a/tests/clocks/input_attr_not_clock/golden.pb_type.xml b/tests/clocks/input_attr_not_clock/golden.pb_type.xml
index 5bc231c..c748dd3 100644
--- a/tests/clocks/input_attr_not_clock/golden.pb_type.xml
+++ b/tests/clocks/input_attr_not_clock/golden.pb_type.xml

@@ -1,6 +1,6 @@
 <?xml version='1.0' encoding='utf-8'?>
-<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="INPUT_ATTR_NOT_CLOCK" num_pb="1">
-  <blif_model>.subckt INPUT_ATTR_NOT_CLOCK</blif_model>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="BLOCK" num_pb="1">
+  <blif_model>.subckt BLOCK</blif_model>
   <input name="a" num_pins="1"/>
   <input name="b" num_pins="1"/>
   <output name="c" num_pins="1"/>

diff --git a/tests/clocks/input_named_clk/README.rst b/tests/clocks/input_named_clk/README.rst
index efbd6be..ed72cd4 100644
--- a/tests/clocks/input_named_clk/README.rst
+++ b/tests/clocks/input_named_clk/README.rst

@@ -5,6 +5,11 @@
 
 .. symbolator:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v
 
+.. verilog-diagram:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v
+   :type: netlistsvg
+   :module: BLOCK
+   :caption: tests/clocks/input_named_clk/input_named_clk.sim.v
+
 .. literalinclude:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v
    :language: verilog
 

diff --git a/tests/clocks/input_named_regex/README.rst b/tests/clocks/input_named_regex/README.rst
index e55f79a..2d6b64b 100644
--- a/tests/clocks/input_named_regex/README.rst
+++ b/tests/clocks/input_named_regex/README.rst

@@ -3,9 +3,14 @@
 
 An input wire can be set as a clock by having `clk` in its name (case insensitive).
 
-.. symbolator:: ../../../tests/clocks/input_named_regex/input_named_regex.sim.v
+.. symbolator:: ../../../tests/clocks/input_named_regex/block.sim.v
 
-.. literalinclude:: ../../../tests/clocks/input_named_regex/input_named_regex.sim.v
+.. verilog-diagram:: ../../../tests/clocks/input_named_regex/block.sim.v
+   :type: netlistsvg
+   :module: BLOCK
+   :caption: tests/clocks/input_named_regex/block.sim.v
+
+.. literalinclude:: ../../../tests/clocks/input_named_regex/block.sim.v
    :language: verilog
 
 As such, the `is_clock` attribute of wires with a variation of `clk` in their name is set to 1.

diff --git a/tests/clocks/input_named_regex/input_named_regex.sim.v b/tests/clocks/input_named_regex/block.sim.v
similarity index 94%
rename from tests/clocks/input_named_regex/input_named_regex.sim.v
rename to tests/clocks/input_named_regex/block.sim.v
index fc20886..bbb5838 100644
--- a/tests/clocks/input_named_regex/input_named_regex.sim.v
+++ b/tests/clocks/input_named_regex/block.sim.v

@@ -9,7 +9,7 @@
  */
 
 (* whitebox *)
-module INPUT_NAMED_REGEX(
+module BLOCK(
     input  wire clk,
     input  wire Clk,
     input  wire CLK,

diff --git a/tests/clocks/input_named_regex/golden.model.xml b/tests/clocks/input_named_regex/golden.model.xml
index 3af62fb..3f5edd2 100644
--- a/tests/clocks/input_named_regex/golden.model.xml
+++ b/tests/clocks/input_named_regex/golden.model.xml

@@ -1,5 +1,5 @@
 <models xmlns:xi="http://www.w3.org/2001/XInclude">
-  <model name="INPUT_NAMED_REGEX">
+  <model name="BLOCK">
     <input_ports>
       <port is_clock="1" name="CLK"/>
       <port is_clock="1" name="Clk"/>

diff --git a/tests/clocks/input_named_regex/golden.pb_type.xml b/tests/clocks/input_named_regex/golden.pb_type.xml
index f7f1500..2edf093 100644
--- a/tests/clocks/input_named_regex/golden.pb_type.xml
+++ b/tests/clocks/input_named_regex/golden.pb_type.xml

@@ -1,6 +1,6 @@
 <?xml version='1.0' encoding='utf-8'?>
-<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="INPUT_NAMED_REGEX" num_pb="1">
-  <blif_model>.subckt INPUT_NAMED_REGEX</blif_model>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="BLOCK" num_pb="1">
+  <blif_model>.subckt BLOCK</blif_model>
   <clock name="CLK" num_pins="1"/>
   <clock name="Clk" num_pins="1"/>
   <clock name="clk" num_pins="1"/>

diff --git a/tests/clocks/multiple_inputs_named_clk/README.rst b/tests/clocks/multiple_inputs_named_clk/README.rst
index 8bdcd76..3723df2 100644
--- a/tests/clocks/multiple_inputs_named_clk/README.rst
+++ b/tests/clocks/multiple_inputs_named_clk/README.rst

@@ -5,6 +5,11 @@
 
 .. symbolator:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v
 
+.. verilog-diagram:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v
+   :type: netlistsvg
+   :module: BLOCK
+   :caption: tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v
+
 .. literalinclude:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v
    :language: verilog
 

diff --git a/tests/clocks/multiple_outputs_named_clk/README.rst b/tests/clocks/multiple_outputs_named_clk/README.rst
index 3376756..2bb9000 100644
--- a/tests/clocks/multiple_outputs_named_clk/README.rst
+++ b/tests/clocks/multiple_outputs_named_clk/README.rst

@@ -1,10 +1,15 @@
 Set outputs as clock by name (multiple clock outputs)
-+++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
 `output wire rdclk` and `output wire wrclk` have `clk` in their names, hence are recognized as clock inputs by v2x.
 
 .. symbolator:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v
 
+.. verilog-diagram:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v
+   :type: netlistsvg
+   :module: BLOCK
+   :caption: tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v
+
 .. literalinclude:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v
    :language: verilog
 

diff --git a/tests/clocks/output_attr_clock/README.rst b/tests/clocks/output_attr_clock/README.rst
index 05f9946..2847d32 100644
--- a/tests/clocks/output_attr_clock/README.rst
+++ b/tests/clocks/output_attr_clock/README.rst

@@ -5,6 +5,11 @@
 
 .. symbolator:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v
 
+.. verilog-diagram:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v
+   :type: netlistsvg
+   :module: BLOCK
+   :caption: tests/clocks/output_attr_clock/output_attr_clock.sim.v
+
 .. literalinclude:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v
    :language: verilog
 

diff --git a/tests/clocks/output_named_clk/README.rst b/tests/clocks/output_named_clk/README.rst
index 9cb2878..069c04e 100644
--- a/tests/clocks/output_named_clk/README.rst
+++ b/tests/clocks/output_named_clk/README.rst

@@ -5,6 +5,11 @@
 
 .. symbolator:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v
 
+.. verilog-diagram:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v
+   :type: netlistsvg
+   :module: BLOCK
+   :caption: tests/clocks/output_named_clk/output_named_clk.sim.v
+
 .. literalinclude:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v
    :language: verilog