Hide copyright from verilog code Signed-off-by: Daniel Lim Wee Soong <weesoong.lim@gmail.com>
diff --git a/tests/clocks/dff_comb_one_clock/README.rst b/tests/clocks/dff_comb_one_clock/README.rst index 7fb837d..0e5240e 100644 --- a/tests/clocks/dff_comb_one_clock/README.rst +++ b/tests/clocks/dff_comb_one_clock/README.rst
@@ -12,6 +12,7 @@ .. literalinclude:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v :language: verilog + :start-after: */ The `is_clock` attribute of the `a` port is set to 1, and the ports `b`, `c` and `d` have their `clock` attribute set to `a`.
diff --git a/tests/clocks/dff_one_clock/README.rst b/tests/clocks/dff_one_clock/README.rst index a92197b..8df0b14 100644 --- a/tests/clocks/dff_one_clock/README.rst +++ b/tests/clocks/dff_one_clock/README.rst
@@ -12,6 +12,7 @@ .. literalinclude:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v :language: verilog + :start-after: */ As you can see in the generated model, the `is_clock` attribute of the `a` port is set to 1, while the `b` and `c` ports have their `clock` attribute set to `a`.
diff --git a/tests/clocks/dff_two_clocks/README.rst b/tests/clocks/dff_two_clocks/README.rst index 467cedf..c670361 100644 --- a/tests/clocks/dff_two_clocks/README.rst +++ b/tests/clocks/dff_two_clocks/README.rst
@@ -12,6 +12,7 @@ .. literalinclude:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v :language: verilog + :start-after: */ The `is_clock` attribute of the `c1` and `c2` ports are set to 1, and the ports `a`, `b`, `c`, `o1` and `o2` have their `clock` attribute set to the respective clocks they are driven by.
diff --git a/tests/clocks/input_attr_clock/README.rst b/tests/clocks/input_attr_clock/README.rst index 1f5b031..acda36d 100644 --- a/tests/clocks/input_attr_clock/README.rst +++ b/tests/clocks/input_attr_clock/README.rst
@@ -12,6 +12,7 @@ .. literalinclude:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v :language: verilog + :start-after: */ As such, the `is_clock` attribute of the `a` port is set to 1.
diff --git a/tests/clocks/input_attr_not_clock/README.rst b/tests/clocks/input_attr_not_clock/README.rst index f51f554..5a51c27 100644 --- a/tests/clocks/input_attr_not_clock/README.rst +++ b/tests/clocks/input_attr_not_clock/README.rst
@@ -12,6 +12,7 @@ .. literalinclude:: ../../../tests/clocks/input_attr_not_clock/block.sim.v :language: verilog + :start-after: */ As such, the `is_clock` attribute of the `a` port is not set.
diff --git a/tests/clocks/input_named_clk/README.rst b/tests/clocks/input_named_clk/README.rst index ed72cd4..7d5bdc1 100644 --- a/tests/clocks/input_named_clk/README.rst +++ b/tests/clocks/input_named_clk/README.rst
@@ -12,6 +12,7 @@ .. literalinclude:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v :language: verilog + :start-after: */ As such, the `is_clock` attribute of the `clk` port is set to 1, without needing to set anything else in the verilog code.
diff --git a/tests/clocks/input_named_regex/README.rst b/tests/clocks/input_named_regex/README.rst index 2d6b64b..a781d06 100644 --- a/tests/clocks/input_named_regex/README.rst +++ b/tests/clocks/input_named_regex/README.rst
@@ -12,6 +12,7 @@ .. literalinclude:: ../../../tests/clocks/input_named_regex/block.sim.v :language: verilog + :start-after: */ As such, the `is_clock` attribute of wires with a variation of `clk` in their name is set to 1.
diff --git a/tests/clocks/multiple_inputs_named_clk/README.rst b/tests/clocks/multiple_inputs_named_clk/README.rst index 3723df2..e5a73ac 100644 --- a/tests/clocks/multiple_inputs_named_clk/README.rst +++ b/tests/clocks/multiple_inputs_named_clk/README.rst
@@ -12,6 +12,7 @@ .. literalinclude:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v :language: verilog + :start-after: */ As such, the `is_clock` attribute of the `rdclk` and `wrclk` ports are set to 1.
diff --git a/tests/clocks/multiple_outputs_named_clk/README.rst b/tests/clocks/multiple_outputs_named_clk/README.rst index 2bb9000..f9d00ec 100644 --- a/tests/clocks/multiple_outputs_named_clk/README.rst +++ b/tests/clocks/multiple_outputs_named_clk/README.rst
@@ -12,6 +12,7 @@ .. literalinclude:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v :language: verilog + :start-after: */ As such, the `is_clock` attribute of the `rdclk` and `wrclk` ports are set to 1.
diff --git a/tests/clocks/output_attr_clock/README.rst b/tests/clocks/output_attr_clock/README.rst index 2847d32..e0d6ca1 100644 --- a/tests/clocks/output_attr_clock/README.rst +++ b/tests/clocks/output_attr_clock/README.rst
@@ -12,6 +12,7 @@ .. literalinclude:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v :language: verilog + :start-after: */ As such, the `is_clock` attribute of the `o` port is set to 1.
diff --git a/tests/clocks/output_named_clk/README.rst b/tests/clocks/output_named_clk/README.rst index 069c04e..cfa3677 100644 --- a/tests/clocks/output_named_clk/README.rst +++ b/tests/clocks/output_named_clk/README.rst
@@ -12,6 +12,7 @@ .. literalinclude:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v :language: verilog + :start-after: */ As such, the `is_clock` attribute of the `clk` output port is set to 1.