Fixed comments, consolidated previously re-used code.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

tests/internal_conn/parent.sim.v

diff --git a/tests/internal_conn/parent.sim.v b/tests/internal_conn/parent.sim.v
index 6f9f8df..e071b82 100644
--- a/tests/internal_conn/parent.sim.v
+++ b/tests/internal_conn/parent.sim.v
@@ -7,13 +7,13 @@
   output wire O1
 );
 
-  // A child cell was connected properly
+  // A child cell
   CHILD child (
   .I(I0),
   .O(O0)
   );
 
-  // Interconnect for this wasn't generated!
+  // An internal connection spanning ports of the PARENT cell.
   assign O1 = I1;
 
 endmodule

tests/modes/inv.sim.v

diff --git a/tests/modes/inv.sim.v b/tests/modes/inv.sim.v
index 1753c48..45fd3df 100644
--- a/tests/modes/inv.sim.v
+++ b/tests/modes/inv.sim.v
@@ -5,7 +5,7 @@
     input  wire I;
     output wire O;
 
-    parameter MODE="";
+    parameter MODE="PASSTHROUGH";
 
     // Passthrough (no inversion) mode
     generate if (MODE == "PASSTHROUGH") begin

v2x/vlog_to_pbtype.py

diff --git a/v2x/vlog_to_pbtype.py b/v2x/vlog_to_pbtype.py
index a9cfbaa..4b3fa40 100755
--- a/v2x/vlog_to_pbtype.py
+++ b/v2x/vlog_to_pbtype.py
@@ -356,7 +356,7 @@
 
                     # Find matching nets
                     if out_net == inp_net:
-                        key =  (None, inp_name)
+                        key = (None, inp_name)
                         val = ((None, out_name), {})
                         interconn[key].append(val)
 
@@ -377,12 +377,12 @@
 
 
 def mode_interconnects(mod, mode_name) -> List[(CellPin)]:
-    interconn = []
+    interconn = {}
     for name, width, bits, iodir in mod.ports:
         if iodir == "input":
-            interconn.append(((None, name), (mode_name, name)))
+            interconn[(None, name)] = [((mode_name, name,), {},)]
         else:
-            interconn.append(((mode_name, name), (None, name)))
+            interconn[(mode_name, name)] = [((None, name,), {},)]
     return interconn
 
 
@@ -654,6 +654,7 @@
 
         make_mux_conn(ic_xml, mux_cell, mux_inputs, mux_outputs)
 
+
 def make_leaf_pb(outfile, yj, mod, mod_pname, pb_type_xml):
 
     # As leaf node with "blif_model" set is a site., need to generate timing
@@ -814,41 +815,32 @@
             )
             mode_mod = mode_yj.module(mod.name)
 
+            inter = {}
+
             # The mode has no children. Don't generate a pb_type then. Make
             # only the interconnect instead.
             if len(mode_mod.cells) == 0:
-
-                inter = get_interconnects(mode_yj, mode_mod, smode,[smode])
-                ic_xml = ET.SubElement(mode_xml, "interconnect")
-
-                for (driv_cell, driv_pin), sinks in inter.items():
-                    for (sink_cell, sink_pin), attrs in sinks:
-                        make_direct_conn(
-                            ic_xml,
-                            (driv_cell, driv_pin),
-                            (sink_cell, sink_pin),
-                            attrs)
+                inter.update(get_interconnects(
+                    mode_yj, mode_mod, smode, [smode]))
 
             # The mode has children, recurse
             else:
-
                 make_pb_type(infiles, outfile, mode_yj, mode_mod,
                              True, mode_xml, smode)
+                inter.update(mode_interconnects(mod, smode))
 
-                # if mode pb_type contains interconnect tag,
-                # add new connctions there
-                ic_xml = mode_xml.find("interconnect")
-                print("ic_xml is", ic_xml, file=sys.stderr)
-                if ic_xml is None:
-                    ic_xml = ET.SubElement(mode_xml, "interconnect")
+            # Add or update the interconnect.
+            ic_xml = mode_xml.find("interconnect")
+            if ic_xml is None:
+                ic_xml = ET.SubElement(mode_xml, "interconnect")
 
-                for (driver_cell,
-                     driver_pin), (sink_cell,
-                                   sink_pin) in mode_interconnects(mod, smode):
+            for (driv_cell, driv_pin), sinks in inter.items():
+                for (sink_cell, sink_pin), attrs in sinks:
                     make_direct_conn(
-                        ic_xml, (driver_cell, driver_pin), (sink_cell, sink_pin),
-                        {}
-                    )
+                        ic_xml,
+                        (driv_cell, driv_pin),
+                        (sink_cell, sink_pin),
+                        attrs)
 
     if not modes or mode_processing:
         routing = children = []