Added test for a clock mux/buffer Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

diff --git a/tests/clock_mux/README.md b/tests/clock_mux/README.md
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+# `clock mux` tests
+
+This is an example of modeling a clock mux/buffer which has both clock inputs and outputs. According to the "Primitive Block Timing Modeling Tutorial" section "Clock Buffers & Muxes" of the VTR manual (https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#clock-muxes), a clock buffer or a clock mux has to have its outputs(s) as combinational sinks of clock input(s). This contradicts with how regular sequential blocks (like flip-flops) has to be modeled.
+
+In this example the NO_COMB attribute is used. When it's value is forced to 0 then clock inputs may get combinational_sink annotations.

diff --git a/tests/clock_mux/gmux.sim.v b/tests/clock_mux/gmux.sim.v
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+++ b/tests/clock_mux/gmux.sim.v

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+// A model of a clock multiplexer with two clock inputs, one clock output and
+// a select input.
+
+(* whitebox *)
+module GMUX (IP, IC, IS0, IZ);
+
+    // 1st clock input
+    (* CLOCK, NO_COMB=0 *)
+    input  wire IP;
+
+    // 2nd clock input
+    (* CLOCK, NO_COMB=0 *)
+    input  wire IC;
+
+    // Select input
+    input  wire IS0;
+
+    // Clock output (has to be defined as a regular output port)
+    (* DELAY_CONST_IP="1e-10" *)
+    (* DELAY_CONST_IC="2e-10" *)
+    (* DELAY_CONST_IS0="3e-10" *)
+    output wire IZ;
+
+
+    // Behavioral model:
+    assign IZ = IS0 ? IC : IP;
+
+endmodule

diff --git a/tests/clock_mux/golden.model.xml b/tests/clock_mux/golden.model.xml
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+<models xmlns:xi="http://www.w3.org/2001/XInclude">
+  <model name="GMUX">
+    <input_ports>
+      <port combinational_sink_ports="IZ" is_clock="1" name="IC"/>
+      <port combinational_sink_ports="IZ" is_clock="1" name="IP"/>
+      <port combinational_sink_ports="IZ" name="IS0"/>
+    </input_ports>
+    <output_ports>
+      <port name="IZ"/>
+    </output_ports>
+  </model>
+</models>

diff --git a/tests/clock_mux/golden.pb_type.xml b/tests/clock_mux/golden.pb_type.xml
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+++ b/tests/clock_mux/golden.pb_type.xml

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+<?xml version='1.0' encoding='utf-8'?>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="GMUX" num_pb="1">
+  <blif_model>.subckt GMUX</blif_model>
+  <clock name="IC" num_pins="1"/>
+  <clock name="IP" num_pins="1"/>
+  <input name="IS0" num_pins="1"/>
+  <output name="IZ" num_pins="1"/>
+  <delay_constant in_port="IC" max="2e-10" out_port="IZ"/>
+  <delay_constant in_port="IP" max="1e-10" out_port="IZ"/>
+  <delay_constant in_port="IS0" max="3e-10" out_port="IZ"/>
+</pb_type>