Added the posibility to express cells that are clock buffers/muxes in the way VPR requires to do that.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

v2x/vlog_to_model.py

diff --git a/v2x/vlog_to_model.py b/v2x/vlog_to_model.py
index bcb40ae..ee4240a 100755
--- a/v2x/vlog_to_model.py
+++ b/v2x/vlog_to_model.py
@@ -201,6 +201,7 @@
             clocks = run.list_clocks(infiles, top)
 
             for name, width, bits, iodir in ports:
+                port_attrs = tmod.port_attrs(name)
 
                 # In the end these can be:
                 # - True when != 1
@@ -216,7 +217,6 @@
 
                 is_clock = name in clocks or utils.is_clock_name(name)
 
-                port_attrs = tmod.port_attrs(name)
                 if "CLOCK" in port_attrs:
                     is_clock = int(port_attrs["CLOCK"]) != 0
 
@@ -234,8 +234,7 @@
                     clks = list()
                     for clk in clocks:
                         if is_clock_assoc(
-                           infiles, top, clk, name, iodir,
-                           prefix=select_prefix):
+                           infiles, top, clk, name, iodir):
 
                             clks.append(clk)
                         if clks and no_seq is not True: