Use no-license directive instead of literalinclude with :startafter option Signed-off-by: Daniel Lim Wee Soong <weesoong.lim@gmail.com>
diff --git a/tests/clocks/dff_comb_one_clock/README.rst b/tests/clocks/dff_comb_one_clock/README.rst index ab01cc6..d2df31e 100644 --- a/tests/clocks/dff_comb_one_clock/README.rst +++ b/tests/clocks/dff_comb_one_clock/README.rst
@@ -11,9 +11,8 @@ | -.. literalinclude:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v +.. no-license:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v :language: verilog - :start-after: */ :caption: tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v The ``is_clock`` attribute of the ``a`` port is set to 1, and the ports ``b``, ``c`` and ``d`` have their ``clock`` attribute set to ``a``.
diff --git a/tests/clocks/dff_one_clock/README.rst b/tests/clocks/dff_one_clock/README.rst index 4acbb70..5301f49 100644 --- a/tests/clocks/dff_one_clock/README.rst +++ b/tests/clocks/dff_one_clock/README.rst
@@ -11,9 +11,8 @@ | -.. literalinclude:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v +.. no-license:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v :language: verilog - :start-after: */ :caption: tests/clocks/dff_one_clock/dff_one_clock.sim.v As you can see in the generated model, the ``is_clock`` attribute of the ``a`` port is set to 1, while the ``b`` and ``c`` ports have their ``clock`` attribute set to ``a``.
diff --git a/tests/clocks/dff_two_clocks/README.rst b/tests/clocks/dff_two_clocks/README.rst index 86a9fa7..12c9f9a 100644 --- a/tests/clocks/dff_two_clocks/README.rst +++ b/tests/clocks/dff_two_clocks/README.rst
@@ -11,9 +11,8 @@ | -.. literalinclude:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v +.. no-license:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v :language: verilog - :start-after: */ :caption: tests/clocks/dff_two_clocks/dff_two_clocks.sim.v The ``is_clock`` attribute of the ``c1`` and ``c2`` ports are set to 1, and the ports ``a``, ``b``, ``c``, ``o1`` and ``o2`` have their ``clock`` attribute set to the respective clocks they are driven by.
diff --git a/tests/clocks/input_attr_clock/README.rst b/tests/clocks/input_attr_clock/README.rst index 792c0ff..c1117d2 100644 --- a/tests/clocks/input_attr_clock/README.rst +++ b/tests/clocks/input_attr_clock/README.rst
@@ -7,9 +7,8 @@ | -.. literalinclude:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v +.. no-license:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v :language: verilog - :start-after: */ :caption: tests/clocks/input_attr_clock/input_attr_clock.sim.v As such, the ``is_clock`` attribute of the ``a`` port is set to 1.
diff --git a/tests/clocks/input_attr_not_clock/README.rst b/tests/clocks/input_attr_not_clock/README.rst index b2404e1..40a2f16 100644 --- a/tests/clocks/input_attr_not_clock/README.rst +++ b/tests/clocks/input_attr_not_clock/README.rst
@@ -11,9 +11,8 @@ | -.. literalinclude:: ../../../tests/clocks/input_attr_not_clock/block.sim.v +.. no-license:: ../../../tests/clocks/input_attr_not_clock/block.sim.v :language: verilog - :start-after: */ :caption: tests/clocks/input_attr_not_clock/block.sim.v As such, the ``is_clock`` attribute of the ``a`` port is not set.
diff --git a/tests/clocks/input_named_clk/README.rst b/tests/clocks/input_named_clk/README.rst index ef83375..b0a8ee0 100644 --- a/tests/clocks/input_named_clk/README.rst +++ b/tests/clocks/input_named_clk/README.rst
@@ -7,9 +7,8 @@ | -.. literalinclude:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v +.. no-license:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v :language: verilog - :start-after: */ :caption: tests/clocks/input_named_clk/input_named_clk.sim.v As such, the ``is_clock`` attribute of the ``clk`` port is set to 1, without needing to set anything else in the verilog code.
diff --git a/tests/clocks/input_named_regex/README.rst b/tests/clocks/input_named_regex/README.rst index fd46a7b..04b7eed 100644 --- a/tests/clocks/input_named_regex/README.rst +++ b/tests/clocks/input_named_regex/README.rst
@@ -7,9 +7,8 @@ | -.. literalinclude:: ../../../tests/clocks/input_named_regex/block.sim.v +.. no-license:: ../../../tests/clocks/input_named_regex/block.sim.v :language: verilog - :start-after: */ :caption: tests/clocks/input_named_regex/block.sim.v As such, the ``is_clock`` attribute of wires with a variation of ``clk`` in their name is set to 1.
diff --git a/tests/clocks/multiple_inputs_named_clk/README.rst b/tests/clocks/multiple_inputs_named_clk/README.rst index b71f1d1..3e802b5 100644 --- a/tests/clocks/multiple_inputs_named_clk/README.rst +++ b/tests/clocks/multiple_inputs_named_clk/README.rst
@@ -7,9 +7,8 @@ | -.. literalinclude:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v +.. no-license:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v :language: verilog - :start-after: */ :caption: tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v As such, the ``is_clock`` attribute of the ``rdclk`` and ``wrclk`` ports are set to 1.
diff --git a/tests/clocks/multiple_outputs_named_clk/README.rst b/tests/clocks/multiple_outputs_named_clk/README.rst index fc00979..6c2ef3c 100644 --- a/tests/clocks/multiple_outputs_named_clk/README.rst +++ b/tests/clocks/multiple_outputs_named_clk/README.rst
@@ -7,9 +7,8 @@ | -.. literalinclude:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v +.. no-license:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v :language: verilog - :start-after: */ :caption: tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v As such, the ``is_clock`` attribute of the ``rdclk`` and ``wrclk`` ports are set to 1.
diff --git a/tests/clocks/output_attr_clock/README.rst b/tests/clocks/output_attr_clock/README.rst index 7e8b221..88ba93a 100644 --- a/tests/clocks/output_attr_clock/README.rst +++ b/tests/clocks/output_attr_clock/README.rst
@@ -7,9 +7,8 @@ | -.. literalinclude:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v +.. no-license:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v :language: verilog - :start-after: */ :caption: tests/clocks/output_attr_clock/output_attr_clock.sim.v As such, the ``is_clock`` attribute of the ``o`` port is set to 1.
diff --git a/tests/clocks/output_named_clk/README.rst b/tests/clocks/output_named_clk/README.rst index f859e8b..5a43c72 100644 --- a/tests/clocks/output_named_clk/README.rst +++ b/tests/clocks/output_named_clk/README.rst
@@ -7,9 +7,8 @@ | -.. literalinclude:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v +.. no-license:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v :language: verilog - :start-after: */ :caption: tests/clocks/output_named_clk/output_named_clk.sim.v As such, the ``is_clock`` attribute of the ``clk`` output port is set to 1.