tests: vlog: DFF: update sim.v and golden model

Signed-off-by: Karol Gugala <kgugala@antmicro.com>

tests/fig42-dff/dff.sim.v

diff --git a/tests/fig42-dff/dff.sim.v b/tests/fig42-dff/dff.sim.v
index d9db239..ec209ec 100644
--- a/tests/fig42-dff/dff.sim.v
+++ b/tests/fig42-dff/dff.sim.v
@@ -1,11 +1,19 @@
 (* whitebox *)
-module DFF (d, clk, q);
-	input wire d;
-	input wire clk;
-	output reg q;
+module DFF (D, CLK, Q);
 
-	always @ ( posedge clk ) begin
-		q <= d;
+	input wire CLK;
+
+	(* SETUP="CLK 10e-12" *)
+	(* HOLD="CLK 10e-12" *)
+	(* CLK_TO_Q="CLK 10e-12" *)
+	input wire D;
+
+	(* CLK_TO_Q="CLK 10e-12" *)
+	output reg Q;
+	(* ASSOC_CLOCK="CLK" *)
+
+	always @ ( posedge CLK ) begin
+		Q <= D;
 	end
 
 `ifndef YOSYS

tests/fig42-dff/golden.model.xml

diff --git a/tests/fig42-dff/golden.model.xml b/tests/fig42-dff/golden.model.xml
index e23a72c..e9eb08e 100644
--- a/tests/fig42-dff/golden.model.xml
+++ b/tests/fig42-dff/golden.model.xml
@@ -2,11 +2,11 @@
   <!-- https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#sequential-block-no-internal-paths -->
   <model name="DFF">
     <input_ports>
-      <port name="clk" is_clock="1"/>
-      <port name="d" clock="clk"/>
+      <port name="CLK" is_clock="1"/>
+      <port name="D" clock="CLK"/>
     </input_ports>
     <output_ports>
-      <port name="q" clock="clk"/>
+      <port name="Q" clock="CLK"/>
     </output_ports>
   </model>
 </models>