apply yapf (via format-python target) to the repo Signed-off-by: Elms <elms@freshred.net>
diff --git a/v2x/lib/argparse_extra.py b/v2x/lib/argparse_extra.py index e59e6e9..a2faa9f 100644 --- a/v2x/lib/argparse_extra.py +++ b/v2x/lib/argparse_extra.py
@@ -54,13 +54,15 @@ * 0 """ - def __init__(self, - option_strings, - dest, - default=None, - required=False, - help=None, - metavar=None): + def __init__( + self, + option_strings, + dest, + default=None, + required=False, + help=None, + metavar=None + ): self.orig_option_strings = option_strings new_option_strings = [] for s in option_strings: @@ -78,7 +80,8 @@ choices=None, required=required, help=help, - metavar=metavar) + metavar=metavar + ) def value(self, s): if not s: @@ -99,8 +102,9 @@ setattr(namespace, self.dest, values[0]) def __repr__(self): - return "ActionStoreBool({}, {})".format(self.orig_option_strings, - self.default) + return "ActionStoreBool({}, {})".format( + self.orig_option_strings, self.default + ) if __name__ == "__main__":
diff --git a/v2x/lib/asserts.py b/v2x/lib/asserts.py index a1e28f2..d0cc6ac 100644 --- a/v2x/lib/asserts.py +++ b/v2x/lib/asserts.py
@@ -25,8 +25,9 @@ def assert_not_in(needle, haystack, msg=None): """Assert equal with better error message.""" - assert needle not in haystack, msg or __safe_error("already in", needle, - haystack) + assert needle not in haystack, msg or __safe_error( + "already in", needle, haystack + ) def assert_is(a, b): @@ -34,9 +35,9 @@ assert a is b, __safe_error("is not", a, b) -def assert_type(obj, - cls, - msg="{obj} ({obj!r}) should be a {cls}, not {objcls}"): +def assert_type( + obj, cls, msg="{obj} ({obj!r}) should be a {cls}, not {objcls}" +): """Raise a type error if obj is not an instance of cls.""" if not isinstance(obj, cls): raise TypeError(msg.format(obj=obj, objcls=type(obj), cls=cls)) @@ -56,4 +57,5 @@ assert len( p ) == max_len, "Length check failed!\nl[{}] has {} elements != {} ({!r})\n{!r}".format( - i, len(p), max_len, p, l) + i, len(p), max_len, p, l + )
diff --git a/v2x/lib/mux.py b/v2x/lib/mux.py index fab33a8..e51c7c0 100644 --- a/v2x/lib/mux.py +++ b/v2x/lib/mux.py
@@ -44,7 +44,8 @@ return "output wire" else: raise TypeError( - "Can't convert {} into verilog definition.".format(self)) + "Can't convert {} into verilog definition.".format(self) + ) def direction(self): if self in (self.INPUT, self.SELECT): @@ -53,7 +54,8 @@ return "output" else: raise TypeError( - "Can't convert {} into verilog definition.".format(self)) + "Can't convert {} into verilog definition.".format(self) + ) def __str__(self): return self.value @@ -76,13 +78,15 @@ def getDefinition(self): if self.width == 1: if self.data_width is not None and self.data_width > 1: - return '\t%s [%d:0] %s;\n' % (self.pin_type.verilog(), - self.data_width - 1, self.name) + return '\t%s [%d:0] %s;\n' % ( + self.pin_type.verilog(), self.data_width - 1, self.name + ) else: return '\t%s %s;\n' % (self.pin_type.verilog(), self.name) else: - return '\t%s %s %s;\n' % (self.pin_type.verilog(), self.index, - self.name) + return '\t%s %s %s;\n' % ( + self.pin_type.verilog(), self.index, self.name + ) def pb_type_xml(mux_type, mux_name, pins, subckt=None, num_pb=1, comment=""): @@ -114,8 +118,8 @@ xml.etree.ElementTree pb_type.xml for requested mux """ - assert isinstance(comment, str), "{} {}".format( - type(comment), repr(comment)) + assert isinstance(comment, + str), "{} {}".format(type(comment), repr(comment)) if mux_type == MuxType.LOGIC: if '-' not in mux_name: @@ -123,27 +127,34 @@ else: assert mux_name.startswith( 'BEL_MX-' - ), "Provided mux name has type {} but not BEL_MX!".format(mux_name) + ), "Provided mux name has type {} but not BEL_MX!".format( + mux_name + ) elif mux_type == MuxType.ROUTING: if '-' not in mux_name: mux_name = 'BEL_RX-' + mux_name else: assert mux_name.startswith( 'BEL_RX-' - ), "Provided mux name has type {} but not BEL_MX!".format(mux_name) + ), "Provided mux name has type {} but not BEL_MX!".format( + mux_name + ) else: assert False, "Unknown type {}".format(mux_type) - pb_type_xml = ET.Element('pb_type', { - 'name': mux_name, - 'num_pb': str(num_pb), - }) + pb_type_xml = ET.Element( + 'pb_type', { + 'name': mux_name, + 'num_pb': str(num_pb), + } + ) if mux_type == MuxType.LOGIC: pb_type_xml.attrib['blif_model'] = '.subckt %s' % subckt else: assert not subckt, "Provided subckt={} for non-logic mux!".format( - subckt) + subckt + ) if comment is not None: pb_type_xml.append(ET.Comment(comment)) @@ -155,7 +166,8 @@ continue assert port.width == 1 or port.data_width == 1, 'Only one of width(%d) or data_width(%d) may > 1 for pin %s' % ( - port.width, port.data_width, port.name) + port.width, port.data_width, port.name + ) if port.width == 1 and port.data_width > 1: num_pins = port.data_width @@ -193,11 +205,13 @@ interconnect = ET.SubElement(pb_type_xml, 'interconnect') inputs = [ - "{}.{}".format(mux_name, port.name) for port in pins + "{}.{}".format(mux_name, port.name) + for port in pins if port.pin_type in (MuxPinType.INPUT, ) ] outputs = [ - "{}.{}".format(mux_name, port.name) for port in pins + "{}.{}".format(mux_name, port.name) + for port in pins if port.pin_type in (MuxPinType.OUTPUT, ) ] assert len(outputs) == 1
diff --git a/v2x/mux_gen.py b/v2x/mux_gen.py index 41bea85..19aac8b 100755 --- a/v2x/mux_gen.py +++ b/v2x/mux_gen.py
@@ -22,99 +22,117 @@ parser = argparse.ArgumentParser( description='Generate a MUX wrapper.', fromfile_prefix_chars='@', - prefix_chars='-~') + prefix_chars='-~' +) parser.add_argument( '--verbose', '--no-verbose', action=ActionStoreBool, default=os.environ.get('V', '') == '1', - help="Print lots of information about the generation.") + help="Print lots of information about the generation." +) parser.add_argument('--width', type=int, default=8, help="Width of the MUX.") parser.add_argument( - '--data-width', type=int, default=1, help="data width of the MUX.") + '--data-width', type=int, default=1, help="data width of the MUX." +) parser.add_argument( '--type', choices=['logic', 'routing'], default='logic', - help="Type of MUX.") + help="Type of MUX." +) parser.add_argument( '--split-inputs', action=ActionStoreBool, default=False, - help="Split the inputs into separate signals") + help="Split the inputs into separate signals" +) parser.add_argument( '--split-selects', action=ActionStoreBool, default=False, - help="Split the selects into separate signals") + help="Split the selects into separate signals" +) parser.add_argument( - '--name-mux', type=str, default='MUX', help="Name of the mux.") + '--name-mux', type=str, default='MUX', help="Name of the mux." +) parser.add_argument( '--name-input', type=str, default='I', - help="Name of the input values for the mux.") + help="Name of the input values for the mux." +) parser.name_inputs = parser.add_argument( '--name-inputs', type=str, default=None, - help="Comma deliminator list for the name of each input to the mux (implies --split-inputs)." + help= + "Comma deliminator list for the name of each input to the mux (implies --split-inputs)." ) parser.add_argument( '--name-output', type=str, default='O', - help="Name of the output value for the mux.") + help="Name of the output value for the mux." +) parser.add_argument( '--name-select', type=str, default='S', - help="Name of the select parameter for the mux.") + help="Name of the select parameter for the mux." +) parser.name_selects = parser.add_argument( '--name-selects', type=str, default=None, - help="Comma deliminator list for the name of each select to the mux (implies --split-selects)." + help= + "Comma deliminator list for the name of each select to the mux (implies --split-selects)." ) parser.add_argument( '--order', - choices=[''.join(x) for x in itertools.permutations('ios')] + - [''.join(x) for x in itertools.permutations('io')], + choices=[''.join(x) for x in itertools.permutations('ios') + ] + [''.join(x) for x in itertools.permutations('io')], default='iso', - help="""Order of the arguments for the MUX. (i - Inputs, o - Output, s - Select)""" + help= + """Order of the arguments for the MUX. (i - Inputs, o - Output, s - Select)""" ) parser.add_argument( '--outdir', default=None, - help="""Directory to output generated content too.""") + help="""Directory to output generated content too.""" +) parser.add_argument( '--outfilename', default=None, - help="""Filename to output generated content too.""") + help="""Filename to output generated content too.""" +) parser.add_argument( - '--comment', default=None, help="""Add some type of comment to the mux.""") + '--comment', default=None, help="""Add some type of comment to the mux.""" +) parser.add_argument( - '--num_pb', default=1, help="""Set the num_pb for the mux.""") + '--num_pb', default=1, help="""Set the num_pb for the mux.""" +) parser.add_argument( - '--subckt', default=None, help="""Override the subcircuit name.""") + '--subckt', default=None, help="""Override the subcircuit name.""" +) def main(argv): @@ -154,7 +172,8 @@ if args.data_width > 1 and not args.split_inputs: assert False, "data_width(%d) > 1 requires using split_inputs" % ( - args.data_width) + args.data_width + ) if args.name_inputs: assert_eq(args.name_input, parser.get_default("name_input")) @@ -163,7 +182,8 @@ names = args.name_inputs.split(',') assert len(names) == args.width, "%s input names, but %s needed." % ( - names, args.width) + names, args.width + ) args.name_inputs = names elif args.split_inputs: args.name_inputs = [ @@ -178,9 +198,10 @@ args.split_selects = True names = args.name_selects.split(',') - assert len( - names) == args.width_bits, "%s select names, but %s needed." % ( - names, args.width_bits) + assert len(names + ) == args.width_bits, "%s select names, but %s needed." % ( + names, args.width_bits + ) args.name_selects = names elif args.split_selects: args.name_selects = [ @@ -209,7 +230,9 @@ sim_filename = '%s.sim.v' % args.outfilename output_files = [ - model_xml_filename, pbtype_xml_filename, sim_filename, + model_xml_filename, + pbtype_xml_filename, + sim_filename, ] # ------------------------------------------------------------------------ @@ -221,35 +244,45 @@ if i == 'i': if args.split_inputs: port_names.extend( - mux_lib.ModulePort(mux_lib.MuxPinType.INPUT, - args.name_inputs[ - j], 1, '[%i]' % j, args.data_width) - for j in range(args.width)) + mux_lib.ModulePort( + mux_lib.MuxPinType.INPUT, args.name_inputs[j], 1, + '[%i]' % j, args.data_width + ) for j in range(args.width) + ) else: # verilog range bounds are inclusive and convention is # [<width-1>:0] port_names.append( - mux_lib.ModulePort(mux_lib.MuxPinType.INPUT, - args.name_input, args.width, - '[%i:0]' % (args.width - 1))) + mux_lib.ModulePort( + mux_lib.MuxPinType.INPUT, args.name_input, args.width, + '[%i:0]' % (args.width - 1) + ) + ) elif i == 's': if args.split_selects: port_names.extend( - mux_lib.ModulePort(mux_lib.MuxPinType.SELECT, - args.name_selects[j], 1, '[%i]' % j) - for j in range(args.width_bits)) + mux_lib.ModulePort( + mux_lib.MuxPinType.SELECT, args.name_selects[j], 1, + '[%i]' % j + ) for j in range(args.width_bits) + ) else: # verilog range bounds are inclusive and convention is # [<width-1>:0] assert args.name_select is not None port_names.append( - mux_lib.ModulePort(mux_lib.MuxPinType.SELECT, - args.name_select, args.width_bits, - '[%i:0]' % (args.width_bits - 1))) + mux_lib.ModulePort( + mux_lib.MuxPinType.SELECT, args.name_select, + args.width_bits, '[%i:0]' % (args.width_bits - 1) + ) + ) elif i == 'o': port_names.append( - mux_lib.ModulePort(mux_lib.MuxPinType.OUTPUT, args.name_output, - 1, '', args.data_width)) + mux_lib.ModulePort( + mux_lib.MuxPinType.OUTPUT, args.name_output, 1, '', + args.data_width + ) + ) # ------------------------------------------------------------------------ # Generate the sim.v Verilog module @@ -271,14 +304,16 @@ f.write("/* ") f.write("\n * ".join(generated_with.splitlines())) f.write("\n */\n\n") - f.write('`include "%s/%s/%smux%i/%smux%i.sim.v"\n' % ( - mux_dir, - 'logic', - '', - args.width, - '', - args.width, - )) + f.write( + '`include "%s/%s/%smux%i/%smux%i.sim.v"\n' % ( + mux_dir, + 'logic', + '', + args.width, + '', + args.width, + ) + ) f.write("\n") f.write('(* blackbox *) (* CLASS="%s" *)\n' % mux_class) f.write("module %s(%s);\n" % (args.name_mux, ", ".join(module_args))) @@ -296,8 +331,9 @@ f.write("\n") if args.data_width > 1: f.write('\tgenvar\tii;\n') - f.write('\tfor(ii=0; ii<%d; ii++) begin: bitmux\n' % - (args.data_width)) + f.write( + '\tfor(ii=0; ii<%d; ii++) begin: bitmux\n' % (args.data_width) + ) f.write('\tMUX%s mux (\n' % args.width) for i in range(0, args.width): @@ -377,12 +413,14 @@ ET.SubElement( input_ports, 'port', { 'name': - port.name, + port.name, 'combinational_sink_ports': - ' '.join( - port.name for port in port_names - if port.pin_type in (mux_lib.MuxPinType.OUTPUT, )), - }) + ' '.join( + port.name for port in port_names if + port.pin_type in (mux_lib.MuxPinType.OUTPUT, ) + ), + } + ) elif port.pin_type in (mux_lib.MuxPinType.OUTPUT, ): ET.SubElement(output_ports, 'port', {'name': port.name})