Fixed comments and return type spec.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

tests/internal_conn/parent.sim.v

diff --git a/tests/internal_conn/parent.sim.v b/tests/internal_conn/parent.sim.v
index e071b82..f837c7b 100644
--- a/tests/internal_conn/parent.sim.v
+++ b/tests/internal_conn/parent.sim.v
@@ -7,13 +7,12 @@
   output wire O1
 );
 
-  // A child cell
   CHILD child (
   .I(I0),
   .O(O0)
   );
 
-  // An internal connection spanning ports of the PARENT cell.
+  // An direct connection from an input to the output pins.
   assign O1 = I1;
 
 endmodule

v2x/vlog_to_pbtype.py

diff --git a/v2x/vlog_to_pbtype.py b/v2x/vlog_to_pbtype.py
index 4b3fa40..26b03a2 100755
--- a/v2x/vlog_to_pbtype.py
+++ b/v2x/vlog_to_pbtype.py
@@ -376,7 +376,7 @@
     return interconn
 
 
-def mode_interconnects(mod, mode_name) -> List[(CellPin)]:
+def mode_interconnects(mod, mode_name) -> Dict[CellPin, List[CellPin]]:
     interconn = {}
     for name, width, bits, iodir in mod.ports:
         if iodir == "input":