Sign in
◑
Theme
foss-fpga-tools
/
python-symbiflow-v2x
/
b17cebc93d624eec4b952da7ee618ddb32e8f7f6
/
.
/
tests
/
internal_conn
/
child
/
child.sim.v
blob: e6aee4423c156254deee152bc5c5ee2aac829006 [
file
]
(*
blackbox
*)
module
CHILD
(
input wire I
,
output wire O
);
endmodule