Final documentation fixes Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/tests/dsp/dsp_inout_registered_dualclk/README.rst b/tests/dsp/dsp_inout_registered_dualclk/README.rst index e50e497..f0f8029 100644 --- a/tests/dsp/dsp_inout_registered_dualclk/README.rst +++ b/tests/dsp/dsp_inout_registered_dualclk/README.rst
@@ -1,4 +1,3 @@ - DSP-style block with inputs and outputs registered using separate clocks ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
diff --git a/tests/gates/README.rst b/tests/gates/README.rst index 85c8997..8a3b79e 100644 --- a/tests/gates/README.rst +++ b/tests/gates/README.rst
@@ -1,9 +1,9 @@ .. Gates -These are some gates -==================== +Basic logic gates +================= -The following shows some examples taken from the tests +These are some basic logic gates. NOT, AND and NOR are modeled as primitives while XOR is made up of 5 NOR gates. .. toctree:: not/README.rst
diff --git a/tests/vtr/full-adder/README.rst b/tests/vtr/full-adder/README.rst index 7f14b68..e9d7000 100644 --- a/tests/vtr/full-adder/README.rst +++ b/tests/vtr/full-adder/README.rst
@@ -1,10 +1,10 @@ Full Adder Example ++++++++++++++++++ -An example of the classical combinational `"full adder" <https://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder>`_ circuit shown in |fig59|_. +An example of the classical combinational `"full adder" <https://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder>`_ circuit shown in |fig60|_ of the `"Combinational block" <https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#combinational-block>`_ section in the Primitive Block Timing Modeling Tutorial of the Verilog to Routing documentation and reproduced below. -.. |fig59| replace:: ``Figure 59 - Full Adder`` -.. _fig59: https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#combinational-block +.. |fig60| replace:: ``Figure 60 - Full Adder`` +.. _fig60: https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#combinational-block .. image:: full-adder.svg :alt: Figure 59 from Verilog to Routing Documentation
diff --git a/tests/vtr/lutff-pair/README.rst b/tests/vtr/lutff-pair/README.rst index 6454c41..0c1961f 100644 --- a/tests/vtr/lutff-pair/README.rst +++ b/tests/vtr/lutff-pair/README.rst
@@ -1,7 +1,7 @@ LUT with FlipFlop Example +++++++++++++++++++++++++ -An example of the classical LUT with FlipFlop pair shown in |fig31|_ demonstrating the `<pack_pattern>` tag. +An example of the classical LUT with FlipFlop pair shown in |fig31|_ of the `"Architecture Reference" <https://docs.verilogtorouting.org/en/latest/arch/reference/#architecture-reference>`_ section of the Verilog to Routing Documentation demonstrating the `<pack_pattern>` tag. .. |fig31| replace:: ``Figure 31 - Pack Pattern Example`` .. _fig31: https://docs.verilogtorouting.org/en/latest/arch/reference/#id35