Extracted a function for generating mux from the main of mux_gen Signed-off-by: Grzegorz Latosinski <glatosinski@antmicro.com>
diff --git a/v2x/mux_gen.py b/v2x/mux_gen.py index 2ae6908..f24950f 100755 --- a/v2x/mux_gen.py +++ b/v2x/mux_gen.py
@@ -136,11 +136,28 @@ ) -def main(argv): - args = parser.parse_args() - +def mux_gen(argv='Python function', + width=8, + data_width=1, + datatype='logic', + split_inputs=False, + split_selects=False, + name_mux='MUX', + name_input='I', + name_inputs=None, + name_output='O', + name_select='S', + name_selects=None, + order='iso', + outdir=None, + outfilename=None, + comment=None, + num_pb=1, + subckt=None, + verbose=False + ): def output_block(name, s): - if args.verbose: + if verbose: print() print(name, '-' * (75 - (len(name) + 1))) print(s, end="") @@ -148,7 +165,7 @@ print() print('-' * 75) - args.width_bits = mux_lib.clog2(args.width) + width_bits = mux_lib.clog2(width) def normpath(p, to=None): p = os.path.realpath(os.path.abspath(p)) @@ -158,54 +175,57 @@ mypath = normpath(__file__) - if not args.outdir: - outdir = os.path.join(".", args.name_mux.lower()) - else: - outdir = args.outdir + if not outdir: + outdir = os.path.join(".", name_mux.lower()) outdir = normpath(outdir) mydir = normpath(os.path.dirname(mypath), to=outdir) mux_dir = normpath(os.path.join(mydir, '..', 'vpr', 'muxes'), to=outdir) - if args.data_width > 1 and not args.split_inputs: + if data_width > 1 and not split_inputs: assert False, "data_width(%d) > 1 requires using split_inputs" % ( - args.data_width + data_width ) - if args.name_inputs: - assert_eq(args.name_input, parser.get_default("name_input")) - args.name_input = None - args.split_inputs = True + name_input_default = 'I' + name_inputs_default = None + name_select_default = 'S' + name_selects_default = None - names = args.name_inputs.split(',') - assert len(names) == args.width, "%s input names, but %s needed." % ( - names, args.width + if name_inputs: + assert_eq(name_input, name_input_default) + name_input = None + split_inputs = True + + names = name_inputs.split(',') + assert len(names) == width, "%s input names, but %s needed." % ( + names, width ) - args.name_inputs = names - elif args.split_inputs: - args.name_inputs = [ - args.name_input + str(i) for i in range(args.width) + name_inputs = names + elif split_inputs: + name_inputs = [ + name_input + str(i) for i in range(width) ] - parser.name_inputs.default = args.name_inputs - assert_eq(parser.get_default("name_inputs"), args.name_inputs) + name_inputs_default = name_inputs + assert_eq(name_inputs_default, name_inputs) - if args.name_selects: - assert_eq(args.name_select, parser.get_default("name_select")) - args.name_select = None - args.split_selects = True + if name_selects: + assert_eq(name_select, name_select_default) + name_select = None + split_selects = True - names = args.name_selects.split(',') - assert len(names) == args.width_bits, ( - "%s select names, but %s needed." % (names, args.width_bits) + names = name_selects.split(',') + assert len(names) == width_bits, ( + "%s select names, but %s needed." % (names, width_bits) ) - args.name_selects = names - elif args.split_selects: - args.name_selects = [ - args.name_select + str(i) for i in range(args.width_bits) + name_selects = names + elif split_selects: + name_selects = [ + name_select + str(i) for i in range(width_bits) ] - parser.name_selects.default = args.name_selects - assert_eq(parser.get_default("name_selects"), args.name_selects) + name_selects.default = name_selects + assert_eq(name_selects_default, name_selects) os.makedirs(outdir, exist_ok=True) @@ -219,72 +239,72 @@ Generated with %s """ % "\n".join(argv).replace('--', '~~') - if not args.outfilename: - args.outfilename = args.name_mux.lower() + if not outfilename: + outfilename = name_mux.lower() - model_xml_filename = '%s.model.xml' % args.outfilename - pbtype_xml_filename = '%s.pb_type.xml' % args.outfilename - sim_filename = '%s.sim.v' % args.outfilename + model_xml_filename = '%s.model.xml' % outfilename + pbtype_xml_filename = '%s.pb_type.xml' % outfilename + sim_filename = '%s.sim.v' % outfilename # ------------------------------------------------------------------------ # Work out the port and their names # ------------------------------------------------------------------------ port_names = [] - for i in args.order: + for i in order: if i == 'i': - if args.split_inputs: + if split_inputs: port_names.extend( mux_lib.ModulePort( - mux_lib.MuxPinType.INPUT, args.name_inputs[j], 1, - '[%i]' % j, args.data_width - ) for j in range(args.width) + mux_lib.MuxPinType.INPUT, name_inputs[j], 1, + '[%i]' % j, data_width + ) for j in range(width) ) else: # verilog range bounds are inclusive and convention is # [<width-1>:0] port_names.append( mux_lib.ModulePort( - mux_lib.MuxPinType.INPUT, args.name_input, args.width, - '[%i:0]' % (args.width - 1) + mux_lib.MuxPinType.INPUT, name_input, width, + '[%i:0]' % (width - 1) ) ) elif i == 's': - if args.split_selects: + if split_selects: port_names.extend( mux_lib.ModulePort( - mux_lib.MuxPinType.SELECT, args.name_selects[j], 1, + mux_lib.MuxPinType.SELECT, name_selects[j], 1, '[%i]' % j - ) for j in range(args.width_bits) + ) for j in range(width_bits) ) else: # verilog range bounds are inclusive and convention is # [<width-1>:0] - assert args.name_select is not None + assert name_select is not None port_names.append( mux_lib.ModulePort( - mux_lib.MuxPinType.SELECT, args.name_select, - args.width_bits, '[%i:0]' % (args.width_bits - 1) + mux_lib.MuxPinType.SELECT, name_select, + width_bits, '[%i:0]' % (width_bits - 1) ) ) elif i == 'o': port_names.append( mux_lib.ModulePort( - mux_lib.MuxPinType.OUTPUT, args.name_output, 1, '', - args.data_width + mux_lib.MuxPinType.OUTPUT, name_output, 1, '', + data_width ) ) # ------------------------------------------------------------------------ # Generate the techmap Verilog module # ------------------------------------------------------------------------ - techmap_filename = '%s.techmap.v' % args.outfilename + techmap_filename = '%s.techmap.v' % outfilename techmap_pathname = os.path.join(outdir, techmap_filename) - if args.type == 'routing': + if datatype == 'routing': with open(techmap_pathname, "w") as f: module_args = [] for port in port_names: - if (args.type == 'routing' and + if (datatype == 'routing' and port.pin_type == mux_lib.MuxPinType.SELECT): continue module_args.append(port.name) @@ -295,7 +315,7 @@ f.write( "module %s(%s);\n" % - (args.name_mux.upper(), ", ".join(module_args)) + (name_mux.upper(), ", ".join(module_args)) ) f.write('\tparameter MODE = "";\n') @@ -337,12 +357,12 @@ with open(sim_pathname, "w") as f: module_args = [] for port in port_names: - if (args.type == 'routing' and + if (datatype == 'routing' and port.pin_type == mux_lib.MuxPinType.SELECT): continue module_args.append(port.name) - mux_class = {'logic': 'mux', 'routing': 'routing'}[args.type] + mux_class = {'logic': 'mux', 'routing': 'routing'}[datatype] f.write("/* ") f.write("\n * ".join(generated_with.splitlines())) @@ -350,21 +370,21 @@ f.write("`default_nettype none\n") f.write("\n") - if args.type != 'routing': + if datatype != 'routing': f.write( '`include "%s/%s/%smux%i/%smux%i.sim.v"\n' % ( mux_dir, 'logic', '', - args.width, + width, '', - args.width, + width, ) ) f.write("\n") f.write('(* CLASS="%s" *)\n' % mux_class) - if args.type == 'routing': + if datatype == 'routing': modes = [ port.name for port in port_names @@ -383,29 +403,29 @@ f.write('(* whitebox *)\n') f.write( "module %s(%s);\n" % - (args.name_mux.upper(), ", ".join(module_args)) + (name_mux.upper(), ", ".join(module_args)) ) previous_type = None for port in port_names: if previous_type != port.pin_type: f.write("\n") previous_type = port.pin_type - if (args.type == 'routing' and + if (datatype == 'routing' and port.pin_type == mux_lib.MuxPinType.SELECT): f.write('\tparameter MODE = "";\n') else: f.write(port.getDefinition()) f.write("\n") - if args.data_width > 1: + if data_width > 1: f.write('\tgenvar\tii;\n') f.write( - '\tfor(ii=0; ii<%d; ii++) begin: bitmux\n' % (args.data_width) + '\tfor(ii=0; ii<%d; ii++) begin: bitmux\n' % (data_width) ) - if args.type == 'logic': - f.write('\tMUX%s mux (\n' % args.width) - for i in range(0, args.width): + if datatype == 'logic': + f.write('\tMUX%s mux (\n' % width) + for i in range(0, width): j = 0 for port in port_names: if port.pin_type != mux_lib.MuxPinType.INPUT: @@ -416,14 +436,14 @@ break if port.width == 1: - if args.data_width > 1: + if data_width > 1: f.write('\t\t.I%i(%s[ii]),\n' % (i, port.name)) else: f.write('\t\t.I%i(%s),\n' % (i, port.name)) else: f.write('\t\t.I%i(%s[%i]),\n' % (i, port.name, i - j)) - for i in range(0, args.width_bits): + for i in range(0, width_bits): j = 0 for port in port_names: if port.pin_type != mux_lib.MuxPinType.SELECT: @@ -443,12 +463,12 @@ continue break assert_eq(port.width, 1) - if args.data_width > 1: + if data_width > 1: f.write('\t\t.O(%s[ii])\n\t);\n' % port.name) else: f.write('\t\t.O(%s)\n\t);\n' % port.name) - elif args.type == 'routing': + elif datatype == 'routing': f.write('\tgenerate\n') for i, mode in enumerate(modes): f.write( @@ -463,23 +483,23 @@ f.write( ('\t\t\t//$error("%s: Invalid routing value %%s ' + '(options are: %s)", MODE);\n') - % (args.name_mux, ", ".join(modes)) + % (name_mux, ", ".join(modes)) ) f.write('\t\tend\n') f.write('\tendgenerate\n') - if args.data_width > 1: + if data_width > 1: f.write('end\n') f.write('endmodule\n') output_block(sim_filename, open(sim_pathname).read()) - if args.type == 'logic': - subckt = args.subckt or args.name_mux + if datatype == 'logic': + subckt = subckt or name_mux assert subckt - elif args.type == 'routing': - assert args.subckt is None + elif datatype == 'routing': + assert subckt is None subckt = None # ------------------------------------------------------------------------ @@ -488,7 +508,7 @@ def xml_comment_indent(n, s): return ("\n" + " " * n).join(s.splitlines() + [""]) - if args.type == 'logic': + if datatype == 'logic': models_xml = ET.Element('models') models_xml.append(ET.Comment(xml_comment_indent(4, xml_comment))) @@ -526,11 +546,11 @@ # ------------------------------------------------------------------------ pb_type_xml = mux_lib.pb_type_xml( - mux_lib.MuxType[args.type.upper()], - args.name_mux, + mux_lib.MuxType[datatype.upper()], + name_mux, port_names, subckt=subckt, - num_pb=args.num_pb, + num_pb=num_pb, comment=xml_comment_indent(4, xml_comment), ) @@ -539,7 +559,32 @@ with open(os.path.join(outdir, pbtype_xml_filename), "w") as f: f.write(pb_type_str) - print("Generated mux {} in {}".format(args.name_mux, outdir)) + print("Generated mux {} in {}".format(name_mux, outdir)) + + +def main(argv): + args = parser.parse_args() + + mux_gen(argv=argv, + width=args.width, + data_width=args.data_width, + datatype=args.type, + split_inputs=args.split_inputs, + split_selects=args.split_selects, + name_mux=args.name_mux, + name_input=args.name_input, + name_inputs=args.name_inputs, + name_output=args.name_output, + name_select=args.name_select, + name_selects=args.name_selects, + order=args.order, + outdir=args.outdir, + outfilename=args.outfilename, + comment=args.comment, + num_pb=args.num_pb, + subckt=args.subckt, + verbose=args.verbose, + ) if __name__ == "__main__":