docs: Working on clocks example documentation. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>

diff --git a/docs/conf.py b/docs/conf.py
index cc769b8..2f67c60 100644
--- a/docs/conf.py
+++ b/docs/conf.py

@@ -43,6 +43,7 @@
     'sphinx.ext.napoleon',
     'sphinx.ext.todo',
     'sphinx_markdown_tables',
+    'symbolator_sphinx',
 ]
 
 # Add any paths that contain templates here, relative to this directory.

diff --git a/docs/index.rst b/docs/index.rst
index 8ca1248..802792a 100644
--- a/docs/index.rst
+++ b/docs/index.rst

@@ -9,10 +9,14 @@
 .. _V2X: http://symbiflow-v2x.readthedocs.io/
 
 .. toctree::
-   :maxdepth: 3
+   :maxdepth: 2
    :glob:
-   :caption: Tests
 
    tests/vtr-examples.rst
-   tests/clocks.rst
    tests/dsp.rst
+
+.. toctree::
+   :maxdepth: 3
+   :glob:
+
+   tests/clocks.rst

diff --git a/docs/requirements.txt b/docs/requirements.txt
index ec9e872..1785ecc 100644
--- a/docs/requirements.txt
+++ b/docs/requirements.txt

@@ -11,3 +11,8 @@
 
 # Markdown cross-reference solver library
 git+https://github.com/SymbiFlow/sphinxcontrib-markdown-symlinks
+
+symbolator
+
+pycairo
+# vext.gi

diff --git a/docs/tests/clocks.rst b/docs/tests/clocks.rst
index a2ab418..68e741b 100644
--- a/docs/tests/clocks.rst
+++ b/docs/tests/clocks.rst

@@ -3,18 +3,18 @@
 Clock Examples
 ==============
 
-FlipFlop Examples
------------------
+Autodetection clock from flipflop
+---------------------------------
 
 .. toctree::
 
-   clocks/dff_comb_one_clock.md
-   clocks/dff_comb_one_clock.md
    clocks/dff_one_clock.md
    clocks/dff_two_clocks.md
 
-Input Clocks
-------------
+.. include:: ../../tests/clocks/dff_comb_one_clock/README.rst
+
+Manual Input Clock
+------------------
 
 .. toctree::
 
@@ -22,8 +22,8 @@
    clocks/input_named_clk.md
    clocks/input_named_rdclk.md
 
-Output Clocks
--------------
+Manual Output Clock
+-------------------
 
 .. toctree::
 

diff --git a/tests/clocks/dff_comb_one_clock/README.rst b/tests/clocks/dff_comb_one_clock/README.rst
new file mode 100644
index 0000000..d1bcf97
--- /dev/null
+++ b/tests/clocks/dff_comb_one_clock/README.rst

@@ -0,0 +1,9 @@
+D-Flipflop with combinational logic
++++++++++++++++++++++++++++++++++++
+
+`input wire a` should be detected as a clock because it drives the flip flop.
+
+.. symbolator:: ../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
+
+.. literalinclude:: ../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
+   :language: verilog