Linked and corrected DSP examples Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/tests/dsp/README.rst b/tests/dsp/README.rst new file mode 100644 index 0000000..627ac28 --- /dev/null +++ b/tests/dsp/README.rst
@@ -0,0 +1,13 @@ +DSP examples +============ + +These are examples of modeling DSP-like complex primitives + +.. toctree:: + dsp_combinational/README.rst + dsp_in_registered/README.rst + dsp_out_registered/README.rst + dsp_inout_registered/README.rst + dsp_inout_registered_dualclk/README.rst + dsp_partial_registered/README.rst + dsp_modes/README.rst
diff --git a/tests/dsp/dsp_combinational/README.md b/tests/dsp/dsp_combinational/README.md deleted file mode 100644 index f565755..0000000 --- a/tests/dsp/dsp_combinational/README.md +++ /dev/null
@@ -1,11 +0,0 @@ -# `dsp_combinational` test - -## Detection of combinational connections - - - [ ] output has combinational connection with input - -## Blackbox detection - - - [ ] model of the leaf `pb_type` is generated - - [ ] leaf `pb_type` XML is generated -
diff --git a/tests/dsp/dsp_combinational/README.rst b/tests/dsp/dsp_combinational/README.rst index 41fa675..0bf3960 100644 --- a/tests/dsp/dsp_combinational/README.rst +++ b/tests/dsp/dsp_combinational/README.rst
@@ -1,25 +1,32 @@ Combinational DSP +++++++++++++++++ -.. symbolator:: ../../tests/dsp/dsp_combinational/dsp_combinational.sim.v +A combinational DSP block capable of multiplication and division. Modeled as "combinational block" according to |fig60|_ of `Primitive Block Timing Modeling Tutorial <https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#primitive-block-timing-modeling-tutorial>`_. -.. verilog-diagram:: ../../tests/dsp/dsp_combinational/dsp_combinational.sim.v +.. |fig60| replace:: ``Figure 60`` +.. _fig60: https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#combinational-block + +| + +.. symbolator:: dsp_combinational.sim.v + +.. verilog-diagram:: dsp_combinational.sim.v :type: netlistsvg :module: DSP_COMBINATIONAL | -.. no-license:: ../../tests/dsp/dsp_combinational/dsp_combinational.sim.v +.. no-license:: dsp_combinational.sim.v :language: verilog :caption: tests/dsp/dsp_combinational/dsp_combinational.sim.v -.. no-license:: ../../tests/dsp/dsp_combinational/golden.model.xml +.. no-license:: dsp_combinational.model.xml :language: xml - :caption: tests/dsp/dsp_combinational/golden.model.xml + :caption: dsp_combinational.model.xml -.. no-license:: ../../tests/dsp/dsp_combinational/golden.pb_type.xml +.. no-license:: dsp_combinational.pb_type.xml :language: xml - :caption: tests/dsp/dsp_combinational/golden.pb_type.xml + :caption: dsp_combinational.pb_type.xml Detection of combinational connections **************************************
diff --git a/tests/dsp/dsp_in_registered/README.rst b/tests/dsp/dsp_in_registered/README.rst index 59a1d94..da05f88 100644 --- a/tests/dsp/dsp_in_registered/README.rst +++ b/tests/dsp/dsp_in_registered/README.rst
@@ -1,27 +1,27 @@ DSP-style block with all inputs registered ++++++++++++++++++++++++++++++++++++++++++ -This uses the model from |fig60|_ and the |dsp_combinational|_ module. +A combinational DSP block with registered inputs. Modeled as a complex block. -.. symbolator:: ../../tests/dsp/dsp_in_registered/dsp_in_registered.sim.v +.. symbolator:: dsp_in_registered.sim.v -.. verilog-diagram:: ../../tests/dsp/dsp_in_registered/dsp_in_registered.sim.v +.. verilog-diagram:: dsp_in_registered.sim.v :type: netlistsvg :module: DSP_IN_REGISTERED | -.. no-license:: ../../tests/dsp/dsp_in_registered/dsp_in_registered.sim.v +.. no-license:: dsp_in_registered.sim.v :language: verilog :caption: tests/dsp/dsp_in_registered/dsp_in_registered.sim.v -.. no-license:: ../../tests/dsp/dsp_in_registered/golden.model.xml +.. no-license:: dsp_in_registered.model.xml :language: xml - :caption: tests/dsp/dsp_in_registered/golden.model.xml + :caption: dsp_in_registered.model.xml -.. no-license:: ../../tests/dsp/dsp_in_registered/golden.pb_type.xml +.. no-license:: dsp_in_registered.pb_type.xml :language: xml - :caption: tests/dsp/dsp_in_registered/golden.pb_type.xml + :caption: dsp_in_registered.pb_type.xml Detection of combinational connections **************************************
diff --git a/tests/dsp/dsp_inout_registered/README.rst b/tests/dsp/dsp_inout_registered/README.rst index 4d8a75d..45a351b 100644 --- a/tests/dsp/dsp_inout_registered/README.rst +++ b/tests/dsp/dsp_inout_registered/README.rst
@@ -1,27 +1,25 @@ DSP-style block with inputs and outputs registered (single clock) +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -This uses the model from |fig60|_ and the |dsp_combinational|_ module. +.. symbolator:: dsp_inout_registered.sim.v -.. symbolator:: ../../tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v - -.. verilog-diagram:: ../../tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v +.. verilog-diagram:: dsp_inout_registered.sim.v :type: netlistsvg :module: DSP_INOUT_REGISTERED | -.. no-license:: ../../tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v +.. no-license:: dsp_inout_registered.sim.v :language: verilog :caption: tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v -.. no-license:: ../../tests/dsp/dsp_inout_registered/golden.model.xml +.. no-license:: dsp_inout_registered.model.xml :language: xml - :caption: tests/dsp/dsp_inout_registered/golden.model.xml + :caption: dsp_inout_registered.model.xml -.. no-license:: ../../tests/dsp/dsp_inout_registered/golden.pb_type.xml +.. no-license:: dsp_inout_registered.pb_type.xml :language: xml - :caption: tests/dsp/dsp_inout_registered/golden.pb_type.xml + :caption: dsp_inout_registered.pb_type.xml Detection of combinational connections **************************************
diff --git a/tests/dsp/dsp_inout_registered_dualclk/README.rst b/tests/dsp/dsp_inout_registered_dualclk/README.rst index 3426d6b..e50e497 100644 --- a/tests/dsp/dsp_inout_registered_dualclk/README.rst +++ b/tests/dsp/dsp_inout_registered_dualclk/README.rst
@@ -2,27 +2,27 @@ DSP-style block with inputs and outputs registered using separate clocks ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -This uses the model from |fig60|_ and the |dsp_combinational|_ module. +A combinational DSP block with registered inputs and outputs. Separate clock is used for inputs and outputs. Modeled as a complex block. -.. symbolator:: ../../tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v +.. symbolator:: dsp_inout_registered_dualclk.sim.v -.. verilog-diagram:: ../../tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v +.. verilog-diagram:: dsp_inout_registered_dualclk.sim.v :type: netlistsvg :module: DSP_INOUT_REGISTERED_DUALCLK | -.. no-license:: ../../tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v +.. no-license:: dsp_inout_registered_dualclk.sim.v :language: verilog :caption: tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v -.. no-license:: ../../tests/dsp/dsp_inout_registered_dualclk/golden.model.xml +.. no-license:: dsp_inout_registered_dualclk.model.xml :language: xml - :caption: tests/dsp/dsp_inout_registered_dualclk/golden.model.xml + :caption: dsp_inout_registered_dualclk.model.xml -.. no-license:: ../../tests/dsp/dsp_inout_registered_dualclk/golden.pb_type.xml +.. no-license:: dsp_inout_registered_dualclk.pb_type.xml :language: xml - :caption: tests/dsp/dsp_inout_registered_dualclk/golden.pb_type.xml + :caption: dsp_inout_registered_dualclk.pb_type.xml Detection of combinational connections **************************************
diff --git a/tests/dsp/dsp_modes/README.rst b/tests/dsp/dsp_modes/README.rst index df20b90..68c8e99 100644 --- a/tests/dsp/dsp_modes/README.rst +++ b/tests/dsp/dsp_modes/README.rst
@@ -9,6 +9,9 @@ * Register on outputs (i.e. |dsp_out_registered|_). * Register on both inputs and outputs (with same clock) (i.e. |dsp_inout_registered|_). +.. |dsp_combinational| replace:: ``dsp_combinational`` +.. _dsp_combinational: #dsp-style-block-with-only-one-input-registered + .. |dsp_partial_registered| replace:: ``dsp_partial_registered`` .. _dsp_partial_registered: #dsp-style-block-with-only-one-input-registered @@ -21,25 +24,25 @@ .. |dsp_inout_registered| replace:: ``dsp_inout_registered`` .. _dsp_inout_registered: #dsp-style-block-with-inputs-and-outputs-registered-single-clock -.. symbolator:: ../../tests/dsp/dsp_modes/dsp_modes.sim.v +.. symbolator:: dsp_modes.sim.v -.. verilog-diagram:: ../../tests/dsp/dsp_modes/dsp_modes.sim.v +.. verilog-diagram:: dsp_modes.sim.v :type: netlistsvg :module: DSP_MODES | -.. no-license:: ../../tests/dsp/dsp_modes/dsp_modes.sim.v +.. no-license:: dsp_modes.sim.v :language: verilog :caption: tests/dsp/dsp_modes/dsp_modes.sim.v -.. no-license:: ../../tests/dsp/dsp_modes/golden.model.xml +.. no-license:: dsp_modes.model.xml :language: xml - :caption: tests/dsp/dsp_modes/golden.model.xml + :caption: dsp_modes.model.xml -.. no-license:: ../../tests/dsp/dsp_modes/golden.pb_type.xml +.. no-license:: dsp_modes.pb_type.xml :language: xml - :caption: tests/dsp/dsp_modes/golden.pb_type.xml + :caption: dsp_modes.pb_type.xml Blackbox detection ******************
diff --git a/tests/dsp/dsp_out_registered/README.rst b/tests/dsp/dsp_out_registered/README.rst index 7e768ee..4baec55 100644 --- a/tests/dsp/dsp_out_registered/README.rst +++ b/tests/dsp/dsp_out_registered/README.rst
@@ -1,27 +1,27 @@ DSP-style block with outputs registered +++++++++++++++++++++++++++++++++++++++ -This uses the model from |fig60|_ and the |dsp_combinational|_ module. +A combinational DSP block with registered outputs. Modeled as a complex block. -.. symbolator:: ../../tests/dsp/dsp_out_registered/dsp_out_registered.sim.v +.. symbolator:: dsp_out_registered.sim.v -.. verilog-diagram:: ../../tests/dsp/dsp_out_registered/dsp_out_registered.sim.v +.. verilog-diagram:: dsp_out_registered.sim.v :type: netlistsvg :module: DSP_OUT_REGISTERED | -.. no-license:: ../../tests/dsp/dsp_out_registered/dsp_out_registered.sim.v +.. no-license:: dsp_out_registered.sim.v :language: verilog :caption: tests/dsp/dsp_out_registered/dsp_out_registered.sim.v -.. no-license:: ../../tests/dsp/dsp_out_registered/golden.model.xml +.. no-license:: dsp_out_registered.model.xml :language: xml - :caption: tests/dsp/dsp_out_registered/golden.model.xml + :caption: dsp_out_registered.model.xml -.. no-license:: ../../tests/dsp/dsp_out_registered/golden.pb_type.xml +.. no-license:: dsp_out_registered.pb_type.xml :language: xml - :caption: tests/dsp/dsp_out_registered/golden.pb_type.xml + :caption: dsp_out_registered.pb_type.xml Detection of combinational connections **************************************
diff --git a/tests/dsp/dsp_partial_registered/README.rst b/tests/dsp/dsp_partial_registered/README.rst index e075bae..69cf4da 100644 --- a/tests/dsp/dsp_partial_registered/README.rst +++ b/tests/dsp/dsp_partial_registered/README.rst
@@ -1,27 +1,27 @@ DSP-style block with only one input registered ++++++++++++++++++++++++++++++++++++++++++++++ -This uses the model from |fig60|_ and the |dsp_combinational|_ module. +A combinational DSP block with all but one registered inputs. Modeled as a complex block. -.. symbolator:: ../../tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v +.. symbolator:: dsp_partial_registered.sim.v -.. verilog-diagram:: ../../tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v +.. verilog-diagram:: dsp_partial_registered.sim.v :type: netlistsvg :module: DSP_PARTIAL_REGISTERED | -.. no-license:: ../../tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v +.. no-license:: dsp_partial_registered.sim.v :language: verilog :caption: tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v -.. no-license:: ../../tests/dsp/dsp_partial_registered/golden.model.xml +.. no-license:: dsp_partial_registered.model.xml :language: xml - :caption: tests/dsp/dsp_partial_registered/golden.model.xml + :caption: dsp_partial_registered.model.xml -.. no-license:: ../../tests/dsp/dsp_partial_registered/golden.pb_type.xml +.. no-license:: dsp_partial_registered.pb_type.xml :language: xml - :caption: tests/dsp/dsp_partial_registered/golden.pb_type.xml + :caption: dsp_partial_registered.pb_type.xml Detection of combinational connections **************************************