utils: flake8 and yapf cleanup

pass PYTHONPATH for v2x to remove modifying syspath

Signed-off-by: Elms <elmsfu@freshred.net>

v2x/mux_gen.py

diff --git a/v2x/mux_gen.py b/v2x/mux_gen.py
index 8236965..26f0de3 100755
--- a/v2x/mux_gen.py
+++ b/v2x/mux_gen.py
@@ -8,10 +8,8 @@
 """
 
 import argparse
-import io
 import itertools
 import lxml.etree as ET
-import math
 import os
 import sys
 
@@ -136,8 +134,6 @@
 
 
 def main(argv):
-    call_args = list(argv)
-
     args = parser.parse_args()
 
     def output_block(name, s):
@@ -168,7 +164,6 @@
 
     mydir = normpath(os.path.dirname(mypath), to=outdir)
     mux_dir = normpath(os.path.join(mydir, '..', 'vpr', 'muxes'), to=outdir)
-    buf_dir = normpath(os.path.join(mydir, '..', 'vpr', 'buf'), to=outdir)
 
     if args.data_width > 1 and not args.split_inputs:
         assert False, "data_width(%d) > 1 requires using split_inputs" % (
@@ -198,10 +193,9 @@
         args.split_selects = True
 
         names = args.name_selects.split(',')
-        assert len(names
-                   ) == args.width_bits, "%s select names, but %s needed." % (
-                       names, args.width_bits
-                   )
+        assert len(names) == args.width_bits, (
+            "%s select names, but %s needed." % (names, args.width_bits)
+        )
         args.name_selects = names
     elif args.split_selects:
         args.name_selects = [
@@ -229,12 +223,6 @@
     pbtype_xml_filename = '%s.pb_type.xml' % args.outfilename
     sim_filename = '%s.sim.v' % args.outfilename
 
-    output_files = [
-        model_xml_filename,
-        pbtype_xml_filename,
-        sim_filename,
-    ]
-
     # ------------------------------------------------------------------------
     # Work out the port and their names
     # ------------------------------------------------------------------------
@@ -288,8 +276,6 @@
     # Generate the sim.v Verilog module
     # ------------------------------------------------------------------------
 
-    defs = {'i': 'input wire', 's': 'input wire', 'o': 'output wire'}
-
     sim_pathname = os.path.join(outdir, sim_filename)
     with open(sim_pathname, "w") as f:
         module_args = []
@@ -298,7 +284,6 @@
                 continue
             module_args.append(port.name)
 
-        mux_prefix = {'logic': '', 'routing': 'r'}[args.type]
         mux_class = {'logic': 'mux', 'routing': 'routing'}[args.type]
 
         f.write("/* ")