blob: 5efc49ac30d21d0b24a2ba8a7e70c0679cc0dd17 [file]
<models xmlns:xi="http://www.w3.org/2001/XInclude">
<xi:include href="../dsp_combinational/dsp_combinational.model.xml" xpointer="xpointer(models/child::node())"/>
<xi:include href="../dsp_inout_registered/dsp_inout_registered.model.xml" xpointer="xpointer(models/child::node())"/>
<model name="DSP_MODES">
<input_ports>
<port clock="clk" combinational_sink_ports="out" name="a"/>
<port clock="clk" combinational_sink_ports="out" name="b"/>
<port is_clock="1" name="clk"/>
<port clock="clk" combinational_sink_ports="out" name="m"/>
</input_ports>
<output_ports>
<port clock="clk" name="out"/>
</output_ports>
</model>
</models>