utils: vlog_to_pbtype: document carry attribute

Signed-off-by: Karol Gugala <kgugala@antmicro.com>

vlog_to_pbtype.py

diff --git a/vlog_to_pbtype.py b/vlog_to_pbtype.py
index 236013a..b0449f6 100755
--- a/vlog_to_pbtype.py
+++ b/vlog_to_pbtype.py
@@ -35,6 +35,8 @@
         delay matrix (semicolons indicate rows). In this format columns specify
         inputs bits and rows specify output bits. This should be applied to the output.
 
+    - `(* carry = ADDER *)` : specify carry chain pack_pattern associated with this wire
+
 The following are allowed on ports:
     - `(* CLOCK *)` : force a given port to be a clock
 
@@ -42,6 +44,8 @@
 
     - `(* PORT_CLASS="clock" *)` : specify the VPR "port_class"
 
+    - `(* carry = ADDER *)` : specify carry chain pack_pattern associated with this port
+
 The Verilog define "PB_TYPE" is set during generation.
 """