| .. SymbiFlow V2X documentation master file | |
| Welcome to SymbiFlow Verilog to XML | |
| ========================================= | |
| `SymbiFlow Verilog to XML`_ `V2X`_ . | |
| .. _SymbiFlow Verilog to XML: https://github.com/SymbiFlow/python-symbiflow-v2x | |
| .. _V2X: http://symbiflow-v2x.readthedocs.io/ | |
| .. toctree:: | |
| :maxdepth: 2 | |
| :glob: | |
| :caption: Tests | |
| Verilog to Routing Examples | |
| - Primitive Block Timing Modeling Tutorial | |
| - tests/fig28-lutff-pair.md | |
| - tests/fig41-full-adder.md | |
| - tests/fig42-dff.md | |
| Clock Example | |
| - FlipFlop Examples | |
| - tests/clocks/dff_comb_one_clock.md | |
| - tests/clocks/dff_one_clock.md | |
| - tests/clocks/dff_two_clocks.md | |
| - Input Clocks | |
| - tests/clocks/input_attr_clock.md | |
| - tests/clocks/input_named_clk.md | |
| - tests/clocks/input_named_rdclk.md | |
| - Output Clocks | |
| - tests/clocks/output_attr_clock.md | |
| - tests/clocks/output_named_clk.md | |
| - tests/clocks/output_named_rdclk.md | |
| - Multiple Clocks | |
| - tests/clocks/multiple_inputs_named_clk.md | |
| - tests/clocks/multiple_outputs_named_clk.md | |
| Carry Example | |
| - tests/carry.md | |
| DSP Examples | |
| - tests/dsp_combinational.md | |
| - tests/dsp_in_registered.md | |
| - tests/dsp_out_registered.md | |
| - tests/dsp_inout_registered.md | |
| - tests/dsp_inout_registered_dualclk.md | |
| - tests/dsp_partial_registered.md | |
| - tests/dsp_modes.md | |
| tests/** |