tests: vlog: lutff-pair: update golden models and pb_types

Signed-off-by: Karol Gugala <kgugala@antmicro.com>

tests/fig28-lutff-pair/ff/golden.model.xml

diff --git a/tests/fig28-lutff-pair/ff/golden.model.xml b/tests/fig28-lutff-pair/ff/golden.model.xml
index 3d65c6d..e9eb08e 100644
--- a/tests/fig28-lutff-pair/ff/golden.model.xml
+++ b/tests/fig28-lutff-pair/ff/golden.model.xml
@@ -1,6 +1,6 @@
 <models xmlns:xi="http://www.w3.org/2001/XInclude">
   <!-- https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#sequential-block-no-internal-paths -->
-  <model name="dff">
+  <model name="DFF">
     <input_ports>
       <port name="CLK" is_clock="1"/>
       <port name="D" clock="CLK"/>

tests/fig28-lutff-pair/lut/golden.model.xml

diff --git a/tests/fig28-lutff-pair/lut/golden.model.xml b/tests/fig28-lutff-pair/lut/golden.model.xml
index 9fd68dd..2059f55 100644
--- a/tests/fig28-lutff-pair/lut/golden.model.xml
+++ b/tests/fig28-lutff-pair/lut/golden.model.xml
@@ -1,7 +1,7 @@
 <models xmlns:xi="http://www.w3.org/2001/XInclude">
   <model name="LUT4">
     <input_ports>
-      <port name="I"/>
+      <port combinational_sink_ports="O" name="I"/>
     </input_ports>
     <output_ports>
       <port name="O"/>

tests/fig28-lutff-pair/lut/golden.pb_type.xml

diff --git a/tests/fig28-lutff-pair/lut/golden.pb_type.xml b/tests/fig28-lutff-pair/lut/golden.pb_type.xml
index c106102..f9cffd2 100644
--- a/tests/fig28-lutff-pair/lut/golden.pb_type.xml
+++ b/tests/fig28-lutff-pair/lut/golden.pb_type.xml
@@ -2,4 +2,7 @@
 <pb_type xmlns:xi="http://www.w3.org/2001/XInclude" blif_model=".subckt LUT4" name="LUT4" num_pb="1">
   <input name="I" num_pins="4"/>
   <output name="O" num_pins="1"/>
+  <delay_matrix in_port="LUT4.I" out_port="LUT4.O" type="max">
+30e-12 30e-12 30e-12 30e-12
+</delay_matrix>
 </pb_type>