mux: added mux class test Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

diff --git a/tests/mux_class/README.md b/tests/mux_class/README.md
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+++ b/tests/mux_class/README.md

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+# Routing Mux tests
+
+This directory contains tests for the `v2x_to_model.py` and `v2x_to_pb_type` tools.
+
+## "mux" Modela Class
+
+ - [ ] modules that have the CLASS attribute defined as `mux` should contain the subckt attribute in the pb\_type.

diff --git a/tests/mux_class/golden.model.xml b/tests/mux_class/golden.model.xml
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+++ b/tests/mux_class/golden.model.xml

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+<models xmlns:xi="http://www.w3.org/2001/XInclude">
+  <model name="MUX_MODEL_NAME">
+    <input_ports>
+      <port combinational_sink_ports="O" name="I0"/>
+      <port combinational_sink_ports="O" name="I1"/>
+      <port combinational_sink_ports="O" name="S"/>
+    </input_ports>
+    <output_ports>
+      <port name="O"/>
+    </output_ports>
+  </model>
+</models>

diff --git a/tests/mux_class/golden.pb_type.xml b/tests/mux_class/golden.pb_type.xml
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+++ b/tests/mux_class/golden.pb_type.xml

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+<?xml version='1.0' encoding='utf-8'?>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" num_pb="1" name="MUX_CLASS">
+  <blif_model>.subckt MUX_MODEL_NAME</blif_model>
+  <input name="I0" num_pins="1"/>
+  <input name="I1" num_pins="1"/>
+  <input name="S" num_pins="1"/>
+  <output name="O" num_pins="1"/>
+  <delay_constant in_port="I0" out_port="O" max="1e-10"/>
+  <delay_constant in_port="I1" out_port="O" max="1e-10"/>
+  <delay_constant in_port="S" out_port="O" max="1e-10"/>
+</pb_type>

diff --git a/tests/mux_class/mux_class.sim.v b/tests/mux_class/mux_class.sim.v
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+++ b/tests/mux_class/mux_class.sim.v

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+`default_nettype none
+
+(* CLASS="mux" *)
+(* MODEL_NAME="MUX_MODEL_NAME" *)
+(* whitebox *)
+module MUX_CLASS(I0, I1, S, O);
+
+	input wire I0;
+	input wire I1;
+
+	input wire S;
+
+	(* DELAY_CONST_I0 = "1e-10" *)
+	(* DELAY_CONST_I1 = "1e-10" *)
+	(* DELAY_CONST_S = "1e-10" *)
+	output wire O;
+
+	assign O = S ? I1 : I0;
+endmodule