tests/clocks/dff_comb_one_clock/README.rst

D-Flipflop with combinational logic
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`input wire a` should be detected as a clock because it drives the flip flop.

.. symbolator:: ../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v

.. literalinclude:: ../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
   :language: verilog