Update file names and xml attributes to follow convention Signed-off-by: Daniel Lim Wee Soong <weesoong.lim@gmail.com>
diff --git a/tests/clocks/dff_two_clocks/golden.model.xml b/tests/clocks/dff_two_clocks/golden.model.xml index 1ca3456..29adb83 100644 --- a/tests/clocks/dff_two_clocks/golden.model.xml +++ b/tests/clocks/dff_two_clocks/golden.model.xml
@@ -2,15 +2,15 @@ <models> <model name="BLOCK"> <input_ports> - <port clock="c1" combinational_sink_ports="o1" name="a"/> - <port clock="c2 c1" combinational_sink_ports="o2 o1" name="b"/> - <port clock="c2" combinational_sink_ports="o2" name="c"/> - <port is_clock="1" name="c1"/> - <port is_clock="1" name="c2"/> + <port name="a" combinational_sink_ports="o1" clock="c1"/> + <port name="b" combinational_sink_ports="o2 o1" clock="c2 c1"/> + <port name="c" combinational_sink_ports="o2" clock="c2"/> + <port name="c1" is_clock="1"/> + <port name="c2" is_clock="1"/> </input_ports> <output_ports> - <port clock="c1" name="o1"/> - <port clock="c2" name="o2"/> + <port name="o1" clock="c1"/> + <port name="o2" clock="c2"/> </output_ports> </model> </models>
diff --git a/tests/clocks/input_attr_not_clock/golden.model.xml b/tests/clocks/input_attr_not_clock/golden.model.xml index 51ff8df..56d6286 100644 --- a/tests/clocks/input_attr_not_clock/golden.model.xml +++ b/tests/clocks/input_attr_not_clock/golden.model.xml
@@ -1,5 +1,5 @@ <models xmlns:xi="http://www.w3.org/2001/XInclude"> - <model name="BLOCK"> + <model name="INPUT_ATTR_NOT_CLOCK"> <input_ports> <port clock="a" combinational_sink_ports="c" name="a"/> <port clock="a" name="b"/>
diff --git a/tests/clocks/input_attr_not_clock/golden.pb_type.xml b/tests/clocks/input_attr_not_clock/golden.pb_type.xml index c748dd3..5bc231c 100644 --- a/tests/clocks/input_attr_not_clock/golden.pb_type.xml +++ b/tests/clocks/input_attr_not_clock/golden.pb_type.xml
@@ -1,6 +1,6 @@ <?xml version='1.0' encoding='utf-8'?> -<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="BLOCK" num_pb="1"> - <blif_model>.subckt BLOCK</blif_model> +<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="INPUT_ATTR_NOT_CLOCK" num_pb="1"> + <blif_model>.subckt INPUT_ATTR_NOT_CLOCK</blif_model> <input name="a" num_pins="1"/> <input name="b" num_pins="1"/> <output name="c" num_pins="1"/>
diff --git a/tests/clocks/input_attr_not_clock/block.sim.v b/tests/clocks/input_attr_not_clock/input_attr_not_clock.sim.v similarity index 93% rename from tests/clocks/input_attr_not_clock/block.sim.v rename to tests/clocks/input_attr_not_clock/input_attr_not_clock.sim.v index 856cdd0..a2f8b11 100644 --- a/tests/clocks/input_attr_not_clock/block.sim.v +++ b/tests/clocks/input_attr_not_clock/input_attr_not_clock.sim.v
@@ -13,7 +13,7 @@ * flop. However, it has the attribute CLOCK set to 0 which should force it * to be a regular input. */ -module BLOCK(a, b, c); +module INPUT_ATTR_NOT_CLOCK(a, b, c); (* CLOCK=0 *) input wire a; input wire b;
diff --git a/tests/clocks/input_named_regex/golden.model.xml b/tests/clocks/input_named_regex/golden.model.xml index 3f5edd2..3af62fb 100644 --- a/tests/clocks/input_named_regex/golden.model.xml +++ b/tests/clocks/input_named_regex/golden.model.xml
@@ -1,5 +1,5 @@ <models xmlns:xi="http://www.w3.org/2001/XInclude"> - <model name="BLOCK"> + <model name="INPUT_NAMED_REGEX"> <input_ports> <port is_clock="1" name="CLK"/> <port is_clock="1" name="Clk"/>
diff --git a/tests/clocks/input_named_regex/golden.pb_type.xml b/tests/clocks/input_named_regex/golden.pb_type.xml index 2edf093..f7f1500 100644 --- a/tests/clocks/input_named_regex/golden.pb_type.xml +++ b/tests/clocks/input_named_regex/golden.pb_type.xml
@@ -1,6 +1,6 @@ <?xml version='1.0' encoding='utf-8'?> -<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="BLOCK" num_pb="1"> - <blif_model>.subckt BLOCK</blif_model> +<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="INPUT_NAMED_REGEX" num_pb="1"> + <blif_model>.subckt INPUT_NAMED_REGEX</blif_model> <clock name="CLK" num_pins="1"/> <clock name="Clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
diff --git a/tests/clocks/input_named_regex/block.sim.v b/tests/clocks/input_named_regex/input_named_regex.sim.v similarity index 94% rename from tests/clocks/input_named_regex/block.sim.v rename to tests/clocks/input_named_regex/input_named_regex.sim.v index bbb5838..fc20886 100644 --- a/tests/clocks/input_named_regex/block.sim.v +++ b/tests/clocks/input_named_regex/input_named_regex.sim.v
@@ -9,7 +9,7 @@ */ (* whitebox *) -module BLOCK( +module INPUT_NAMED_REGEX( input wire clk, input wire Clk, input wire CLK,