Remove netlistsvg diagram for blackbox modules and add pb_type.xml Signed-off-by: Daniel Lim Wee Soong <weesoong.lim@gmail.com>
diff --git a/tests/clocks/dff_comb_one_clock/README.rst b/tests/clocks/dff_comb_one_clock/README.rst index 0e5240e..438f419 100644 --- a/tests/clocks/dff_comb_one_clock/README.rst +++ b/tests/clocks/dff_comb_one_clock/README.rst
@@ -8,13 +8,16 @@ .. verilog-diagram:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v :type: netlistsvg :module: BLOCK - :caption: tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v + +| .. literalinclude:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v The `is_clock` attribute of the `a` port is set to 1, and the ports `b`, `c` and `d` have their `clock` attribute set to `a`. .. literalinclude:: ../../../tests/clocks/dff_comb_one_clock/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/dff_comb_one_clock/golden.model.xml \ No newline at end of file
diff --git a/tests/clocks/dff_one_clock/README.rst b/tests/clocks/dff_one_clock/README.rst index 8df0b14..be7e6ee 100644 --- a/tests/clocks/dff_one_clock/README.rst +++ b/tests/clocks/dff_one_clock/README.rst
@@ -8,13 +8,16 @@ .. verilog-diagram:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v :type: netlistsvg :module: BLOCK - :caption: tests/clocks/dff_one_clock/dff_one_clock.sim.v + +| .. literalinclude:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/dff_one_clock/dff_one_clock.sim.v As you can see in the generated model, the `is_clock` attribute of the `a` port is set to 1, while the `b` and `c` ports have their `clock` attribute set to `a`. .. literalinclude:: ../../../tests/clocks/dff_one_clock/golden.model.xml :language: xml + :caption: tests/clocks/dff_one_clock/golden.model.xml
diff --git a/tests/clocks/dff_two_clocks/README.rst b/tests/clocks/dff_two_clocks/README.rst index c670361..bc64b74 100644 --- a/tests/clocks/dff_two_clocks/README.rst +++ b/tests/clocks/dff_two_clocks/README.rst
@@ -8,13 +8,16 @@ .. verilog-diagram:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v :type: netlistsvg :module: BLOCK - :caption: tests/clocks/dff_two_clocks/dff_two_clocks.sim.v + +| .. literalinclude:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/dff_two_clocks/dff_two_clocks.sim.v The `is_clock` attribute of the `c1` and `c2` ports are set to 1, and the ports `a`, `b`, `c`, `o1` and `o2` have their `clock` attribute set to the respective clocks they are driven by. .. literalinclude:: ../../../tests/clocks/dff_two_clocks/golden.model.xml :language: xml + :caption: tests/clocks/dff_two_clocks/golden.model.xml
diff --git a/tests/clocks/input_attr_clock/README.rst b/tests/clocks/input_attr_clock/README.rst index acda36d..a0f047b 100644 --- a/tests/clocks/input_attr_clock/README.rst +++ b/tests/clocks/input_attr_clock/README.rst
@@ -5,16 +5,15 @@ .. symbolator:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v -.. verilog-diagram:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/input_attr_clock/input_attr_clock.sim.v +| .. literalinclude:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/input_attr_clock/input_attr_clock.sim.v As such, the `is_clock` attribute of the `a` port is set to 1. .. literalinclude:: ../../../tests/clocks/input_attr_clock/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/input_attr_clock/golden.model.xml \ No newline at end of file
diff --git a/tests/clocks/input_attr_not_clock/README.rst b/tests/clocks/input_attr_not_clock/README.rst index 5a51c27..2b2e93d 100644 --- a/tests/clocks/input_attr_not_clock/README.rst +++ b/tests/clocks/input_attr_not_clock/README.rst
@@ -8,13 +8,20 @@ .. verilog-diagram:: ../../../tests/clocks/input_attr_not_clock/block.sim.v :type: netlistsvg :module: BLOCK - :caption: tests/clocks/input_attr_not_clock/block.sim.v + +| .. literalinclude:: ../../../tests/clocks/input_attr_not_clock/block.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/input_attr_not_clock/block.sim.v As such, the `is_clock` attribute of the `a` port is not set. .. literalinclude:: ../../../tests/clocks/input_attr_not_clock/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/input_attr_not_clock/golden.model.xml + +.. literalinclude:: ../../../tests/clocks/input_attr_not_clock/golden.pb_type.xml + :language: xml + :caption: tests/clocks/input_attr_not_clock/golden.pb_type.xml \ No newline at end of file
diff --git a/tests/clocks/input_named_clk/README.rst b/tests/clocks/input_named_clk/README.rst index 7d5bdc1..e3f8580 100644 --- a/tests/clocks/input_named_clk/README.rst +++ b/tests/clocks/input_named_clk/README.rst
@@ -5,16 +5,15 @@ .. symbolator:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v -.. verilog-diagram:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/input_named_clk/input_named_clk.sim.v +| .. literalinclude:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/input_named_clk/input_named_clk.sim.v As such, the `is_clock` attribute of the `clk` port is set to 1, without needing to set anything else in the verilog code. .. literalinclude:: ../../../tests/clocks/input_named_clk/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/input_named_clk/golden.model.xml \ No newline at end of file
diff --git a/tests/clocks/input_named_regex/README.rst b/tests/clocks/input_named_regex/README.rst index a781d06..ab9982a 100644 --- a/tests/clocks/input_named_regex/README.rst +++ b/tests/clocks/input_named_regex/README.rst
@@ -5,16 +5,19 @@ .. symbolator:: ../../../tests/clocks/input_named_regex/block.sim.v -.. verilog-diagram:: ../../../tests/clocks/input_named_regex/block.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/input_named_regex/block.sim.v +| .. literalinclude:: ../../../tests/clocks/input_named_regex/block.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/input_named_regex/block.sim.v As such, the `is_clock` attribute of wires with a variation of `clk` in their name is set to 1. .. literalinclude:: ../../../tests/clocks/input_named_regex/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/input_named_regex/golden.model.xml + +.. literalinclude:: ../../../tests/clocks/input_named_regex/golden.pb_type.xml + :language: xml + :caption: tests/clocks/input_named_regex/golden.pb_type.xml \ No newline at end of file
diff --git a/tests/clocks/multiple_inputs_named_clk/README.rst b/tests/clocks/multiple_inputs_named_clk/README.rst index e5a73ac..1e379ef 100644 --- a/tests/clocks/multiple_inputs_named_clk/README.rst +++ b/tests/clocks/multiple_inputs_named_clk/README.rst
@@ -5,16 +5,15 @@ .. symbolator:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v -.. verilog-diagram:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v +| .. literalinclude:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v As such, the `is_clock` attribute of the `rdclk` and `wrclk` ports are set to 1. .. literalinclude:: ../../../tests/clocks/multiple_inputs_named_clk/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/multiple_inputs_named_clk/golden.model.xml \ No newline at end of file
diff --git a/tests/clocks/multiple_outputs_named_clk/README.rst b/tests/clocks/multiple_outputs_named_clk/README.rst index f9d00ec..2049653 100644 --- a/tests/clocks/multiple_outputs_named_clk/README.rst +++ b/tests/clocks/multiple_outputs_named_clk/README.rst
@@ -5,16 +5,15 @@ .. symbolator:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v -.. verilog-diagram:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v +| .. literalinclude:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v As such, the `is_clock` attribute of the `rdclk` and `wrclk` ports are set to 1. .. literalinclude:: ../../../tests/clocks/multiple_outputs_named_clk/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/multiple_outputs_named_clk/golden.model.xml \ No newline at end of file
diff --git a/tests/clocks/output_attr_clock/README.rst b/tests/clocks/output_attr_clock/README.rst index e0d6ca1..16e75e5 100644 --- a/tests/clocks/output_attr_clock/README.rst +++ b/tests/clocks/output_attr_clock/README.rst
@@ -5,16 +5,15 @@ .. symbolator:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v -.. verilog-diagram:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/output_attr_clock/output_attr_clock.sim.v +| .. literalinclude:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/output_attr_clock/output_attr_clock.sim.v As such, the `is_clock` attribute of the `o` port is set to 1. .. literalinclude:: ../../../tests/clocks/output_attr_clock/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/output_attr_clock/golden.model.xml \ No newline at end of file
diff --git a/tests/clocks/output_named_clk/README.rst b/tests/clocks/output_named_clk/README.rst index cfa3677..4211904 100644 --- a/tests/clocks/output_named_clk/README.rst +++ b/tests/clocks/output_named_clk/README.rst
@@ -5,16 +5,15 @@ .. symbolator:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v -.. verilog-diagram:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/output_named_clk/output_named_clk.sim.v +| .. literalinclude:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/output_named_clk/output_named_clk.sim.v As such, the `is_clock` attribute of the `clk` output port is set to 1. .. literalinclude:: ../../../tests/clocks/output_named_clk/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/output_named_clk/golden.model.xml \ No newline at end of file