tests/vtr/primitives.rst

Primitive Block Timing Modeling Tutorial
========================================

The following shows examples taken from the
`Primitive Block Timing Modeling Tutorial <https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#>`_
in the `Verilog to Routing documentation <https://docs.verilogtorouting.org>`_.

.. toctree::
   dff/README.rst
   full-adder/README.rst
   lutff-pair/README.rst