vpr/ibuf/ibuf.pb_type.xml

<!-- An IO pin found on an FPGA -->
<pb_type name="IBUF" capacity="1">
 <output name="I" num_pins="1"/>
 <pb_type name="PAD" blif_model=".input" num_pb="1">
  <output name="inpad" num_pins="1"/>
  <metadata>
   <meta name="type">bel</meta>
   <meta name="subtype">input</meta>
  </metadata>
 </pb_type>
 <interconnect>
  <direct name="IBUF" input="PAD.inpad" output="IBUF.I" />
 </interconnect>
 <fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0" />
 <pinlocations pattern="custom">
  <loc side="right">IBUF.I</loc>
 </pinlocations>
 <metadata>
  <meta name="type">block</meta>
  <meta name="subtype">tile</meta>
 </metadata>
</pb_type>