quicklogic/pp3/tests/btn_ff/btn_ff.v - symbiflow-arch-defs - Git at Google

 module top(
   input  wire clk,
   input  wire d,
   output reg  q
 );

   always @(posedge clk)
       q <= d;

 endmodule
	module top(
	input wire clk,
	input wire d,
	output reg q
	);

	always @(posedge clk)
	q <= d;

	endmodule