| <?xml version="1.0" encoding="utf-8"?> |
| <!-- |
| XML file specification is primarily to define the mapping of the interface cell ports defined |
| in vpr_arch xml, to the EFPGA IO interface port names. This mapping is required by Symbiflow |
| alongwith architecture definition file i.e. vpr_arch xml file. Symbiflow will process this |
| file and use this information for IO placement and then later on use this to map it with the |
| user-defined pin-mapping file. |
| --> |
| <DEVICE name= "qlf_k4n8_umc22" family="qlf_k4n8" width="26" height="26" z="16"> |
| <IO> |
| <TOP_IO y="25"> |
| <CELL port_name="f2a_i" mapped_name="gfpga_pad_IO_F2A[0:383]" startx="1" endx="24"/> |
| <CELL port_name="a2f_o" mapped_name="gfpga_pad_IO_A2F[0:383]" startx="1" endx="24"/> |
| </TOP_IO> |
| <RIGHT_IO x="25"> |
| <CELL port_name="f2a_i" mapped_name="gfpga_pad_IO_F2A[384:767]" starty="24" endy="1"/> |
| <CELL port_name="a2f_o" mapped_name="gfpga_pad_IO_A2F[384:767]" starty="24" endy="1"/> |
| </RIGHT_IO> |
| <BOTTOM_IO y="0"> |
| <CELL port_name="f2a_i" mapped_name="gfpga_pad_IO_F2A[768:1151]" startx="24" endx="1"/> |
| <CELL port_name="a2f_o" mapped_name="gfpga_pad_IO_A2F[768:1151]" startx="24" endx="1"/> |
| </BOTTOM_IO> |
| <LEFT_IO x="0"> |
| <CELL port_name="f2a_i" mapped_name="gfpga_pad_IO_F2A[1152:1535]" starty="1" endy="24"/> |
| <CELL port_name="a2f_o" mapped_name="gfpga_pad_IO_A2F[1152:1535]" starty="1" endy="24"/> |
| </LEFT_IO> |
| </IO> |
| </DEVICE> |
