| <models xmlns:xi="http://www.w3.org/2001/XInclude"> | |
| <model name="ISERDESE2_NO_IDELAY_VPR"> | |
| <input_ports> | |
| <port is_clock="1" name="CLK"/> | |
| <port is_clock="1" name="CLKB"/> | |
| <port is_clock="1" name="CLKDIV"/> | |
| <port clock="CLKDIV" name="BITSLIP"/> | |
| <!-- This is only correct for NUM_CE = 2 --> | |
| <port clock="CLKDIV" name="CE1"/> | |
| <port clock="CLKDIV" name="CE2"/> | |
| <port clock="CLK" combinational_sink_ports="O" name="D"/> | |
| <port name="DYNCLKDIVPSEL"/> | |
| <port name="DYNCLKDIVSEL"/> | |
| <port name="DYNCLKSEL"/> | |
| <port is_clock="1" name="OCLK"/> | |
| <port is_clock="1" name="OCLKB"/> | |
| <port clock="CLK" name="OFB" combinational_sink_ports="O"/> | |
| <port name="SHIFTIN1"/> | |
| <port name="SHIFTIN2"/> | |
| <port clock="CLKDIV" name="RST"/> | |
| <port combinational_sink_ports="O" name="TFB"/> | |
| </input_ports> | |
| <output_ports> | |
| <port name="O"/> | |
| <port clock="CLKDIV" name="Q1"/> | |
| <port clock="CLKDIV" name="Q2"/> | |
| <port clock="CLKDIV" name="Q3"/> | |
| <port clock="CLKDIV" name="Q4"/> | |
| <port clock="CLKDIV" name="Q5"/> | |
| <port clock="CLKDIV" name="Q6"/> | |
| <port clock="CLKDIV" name="Q7"/> | |
| <port clock="CLKDIV" name="Q8"/> | |
| <port name="SHIFTOUT1"/> | |
| <port name="SHIFTOUT2"/> | |
| </output_ports> | |
| </model> | |
| <model name="ISERDESE2_IDELAY_VPR"> | |
| <input_ports> | |
| <port is_clock="1" name="CLK"/> | |
| <port is_clock="1" name="CLKB"/> | |
| <port is_clock="1" name="CLKDIV"/> | |
| <port clock="CLKDIV" name="BITSLIP"/> | |
| <port clock="CLKDIV" name="CE1"/> | |
| <port clock="CLKDIV" name="CE2"/> | |
| <port clock="CLK" combinational_sink_ports="O" name="DDLY"/> | |
| <port name="DYNCLKDIVPSEL"/> | |
| <port name="DYNCLKDIVSEL"/> | |
| <port name="DYNCLKSEL"/> | |
| <port is_clock="1" name="OCLK"/> | |
| <port is_clock="1" name="OCLKB"/> | |
| <port clock="CLK" name="OFB" combinational_sink_ports="O"/> | |
| <port name="SHIFTIN1"/> | |
| <port name="SHIFTIN2"/> | |
| <port clock="CLKDIV" name="RST"/> | |
| <port combinational_sink_ports="O" name="TFB"/> | |
| </input_ports> | |
| <output_ports> | |
| <port name="O"/> | |
| <port clock="CLKDIV" name="Q1"/> | |
| <port clock="CLKDIV" name="Q2"/> | |
| <port clock="CLKDIV" name="Q3"/> | |
| <port clock="CLKDIV" name="Q4"/> | |
| <port clock="CLKDIV" name="Q5"/> | |
| <port clock="CLKDIV" name="Q6"/> | |
| <port clock="CLKDIV" name="Q7"/> | |
| <port clock="CLKDIV" name="Q8"/> | |
| <port name="SHIFTOUT1"/> | |
| <port name="SHIFTOUT2"/> | |
| </output_ports> | |
| </model> | |
| <model name="IDDR_VPR"> | |
| <input_ports> | |
| <port name="CK" is_clock="1"/> | |
| <port name="CKB" is_clock="1"/> | |
| <port name="CE" clock="CK"/> | |
| <port name="SR"/> | |
| <port name="D" clock="CK"/> | |
| </input_ports> | |
| <output_ports> | |
| <port name="Q1" clock="CK"/> | |
| <port name="Q2" clock="CK"/> | |
| </output_ports> | |
| </model> | |
| </models> |