vpr/pad/pad.pb_type.xml

<!-- An IO pin found on an FPGA -->
<pb_type name="VPR_PAD" capacity="1">
 <input name="outpad" num_pins="1"/>
 <output name="inpad" num_pins="1"/>

 <!-- IO operating as an input -->
 <mode name="PAD_IS_INPUT">
  <pb_type name="INPUT" blif_model=".input" num_pb="1">
   <output name="inpad" num_pins="1"/>
   <metadata>
    <meta name="type">bel</meta>
    <meta name="subtype">input</meta>
   </metadata>
  </pb_type>
  <interconnect>
   <direct name="INPUT" input="INPUT.inpad" output="VPR_PAD.inpad">
    <delay_constant max="4.243e-11" in_port="INPUT.inpad" out_port="VPR_PAD.inpad"/>
   </direct>
  </interconnect>
 </mode>

 <!-- IO operating as an output -->
 <mode name="PAD_IS_OUTPUT">
  <pb_type name="OUTPUT" blif_model=".output" num_pb="1">
   <input name="outpad" num_pins="1"/>
   <metadata>
    <meta name="type">bel</meta>
    <meta name="subtype">output</meta>
   </metadata>
  </pb_type>
  <interconnect>
   <direct name="OUTPUT" input="VPR_PAD.outpad" output="OUTPUT.outpad">
    <delay_constant max="1.394e-11" in_port="VPR_PAD.outpad" out_port="OUTPUT.outpad"/>
   </direct>
  </interconnect>
 </mode>

 <!-- FIXME - Should have a IO operating as bi-directional -->

 <!-- IO pins are never connected to the fabric, they are connected to a platform specific IO tile -->
 <fc in_type="frac" in_val="1" out_type="frac" out_val="1"/>

 <!--
  IOs go on the periphery of the FPGA/

  Currently for consistency make it physically equivalent on all sides so
  that only one definition of I/Os is needed.

  If I do not make a physically equivalent definition, then we need to 4
  different pin definitions (one for each side of the FPGA).
 -->
 <pinlocations pattern="custom">
  <loc side="right">VPR_PAD.outpad VPR_PAD.inpad</loc>
 </pinlocations>
 <metadata>
  <meta name="type">block</meta>
  <meta name="subtype">tile</meta>
 </metadata>
</pb_type>