Merge pull request #3322 from ad-astra-et-ultra/dsp48e1_support
Dsp48e1 support for XILINX
diff --git a/utils/update_arch_timings.py b/utils/update_arch_timings.py
index 7aec657..6755ec7 100755
--- a/utils/update_arch_timings.py
+++ b/utils/update_arch_timings.py
@@ -114,7 +114,7 @@
def get_timing(cell, delay, corner, speed_type):
"""
- Gets timing for a particular cornet case. If not fount then chooses
+ Gets timing for a particular corner case. If not found then chooses
the next best one.
"""
entries = cell[delay]['delay_paths'][corner.lower()]
diff --git a/xilinx/common/primitives/dsp48e1/CMakeLists.txt b/xilinx/common/primitives/dsp48e1/CMakeLists.txt
index 4e58dff..973990c 100644
--- a/xilinx/common/primitives/dsp48e1/CMakeLists.txt
+++ b/xilinx/common/primitives/dsp48e1/CMakeLists.txt
@@ -1,17 +1,2 @@
-add_subdirectory(nreg)
-add_subdirectory(alu)
-add_subdirectory(alumode_mux)
-add_subdirectory(carryinsel_logic)
-add_subdirectory(carryinsel_mux)
-add_subdirectory(creg_mux)
-add_subdirectory(dual_ad_preadder)
-add_subdirectory(dual_b_reg)
-add_subdirectory(inmode_mux)
-add_subdirectory(mult25x18)
-add_subdirectory(mult_mux)
-add_subdirectory(opmode_mux)
-add_subdirectory(xmux)
-add_subdirectory(ymux)
-add_subdirectory(zmux)
-add_file_target(FILE dsp48e1.sim.v SCANNER_TYPE verilog)
-v2x(NAME dsp48e1 SRCS dsp48e1.sim.v)
+add_file_target(FILE dsp48e1.model.xml SCANNER_TYPE xml)
+add_file_target(FILE dsp48e1.pb_type.xml SCANNER_TYPE xml)
diff --git a/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml b/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml
new file mode 100644
index 0000000..8148752
--- /dev/null
+++ b/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml
@@ -0,0 +1,57 @@
+<models>
+<model name="DSP48E1_VPR">
+<input_ports>
+<port clock="CLK" name="A" combinational_sink_ports="ACOUT CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+<port clock="CLK" name="B" combinational_sink_ports="BCOUT CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+<port clock="CLK" name="C" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+<port clock="CLK" name="D" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+<port clock="CLK" name="OPMODE" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+<port clock="CLK" name="ALUMODE" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+<port clock="CLK" name="CARRYIN" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+<port clock="CLK" name="CARRYINSEL" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+<port clock="CLK" name="INMODE" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+<port clock="CLK" name="CEA1"/>
+<port clock="CLK" name="CEA2"/>
+<port clock="CLK" name="CEB1"/>
+<port clock="CLK" name="CEB2"/>
+<port clock="CLK" name="CEC"/>
+<port clock="CLK" name="CED"/>
+<port clock="CLK" name="CEM"/>
+<port clock="CLK" name="CEP"/>
+<port clock="CLK" name="CEAD"/>
+<port clock="CLK" name="CEALUMODE"/>
+<port clock="CLK" name="CECTRL"/>
+<port clock="CLK" name="CECARRYIN"/>
+<port clock="CLK" name="CEINMODE"/>
+<port clock="CLK" name="RSTA"/>
+<port clock="CLK" name="RSTB"/>
+<port clock="CLK" name="RSTC"/>
+<port clock="CLK" name="RSTD"/>
+<port clock="CLK" name="RSTM"/>
+<port clock="CLK" name="RSTP"/>
+<port clock="CLK" name="RSTCTRL"/>
+<port clock="CLK" name="RSTALLCARRYIN"/>
+<port clock="CLK" name="RSTALUMODE"/>
+<port clock="CLK" name="RSTINMODE"/>
+<port is_clock="1" name="CLK"/>
+<port clock="CLK" name="ACIN" combinational_sink_ports="ACOUT CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+<port clock="CLK" name="BCIN" combinational_sink_ports="BCOUT CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+<port clock="CLK" name="PCIN" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+<port clock="CLK" name="CARRYCASCIN" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+<port clock="CLK" name="MULTSIGNIN" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
+</input_ports>
+<output_ports>
+<port clock="CLK" name="ACOUT"/>
+<port clock="CLK" name="BCOUT"/>
+<port clock="CLK" name="PCOUT"/>
+<port clock="CLK" name="P"/>
+<port clock="CLK" name="CARRYOUT"/>
+<port clock="CLK" name="CARRYCASCOUT"/>
+<port clock="CLK" name="MULTSIGNOUT"/>
+<port clock="CLK" name="PATTERNDETECT"/>
+<port clock="CLK" name="PATTERNBDETECT"/>
+<port clock="CLK" name="OVERFLOW"/>
+<port clock="CLK" name="UNDERFLOW"/>
+</output_ports>
+</model>
+</models>
diff --git a/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml b/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml
new file mode 100644
index 0000000..45b063e
--- /dev/null
+++ b/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml
@@ -0,0 +1,462 @@
+<pb_type name="DSP48" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">
+<clock name="CLK" num_pins="1"/>
+<input name="A" num_pins="30"/>
+<input name="B" num_pins="18"/>
+<input name="C" num_pins="48"/>
+<input name="D" num_pins="25"/>
+<input name="OPMODE" num_pins="7"/>
+<input name="ALUMODE" num_pins="4"/>
+<input name="CARRYIN" num_pins="1"/>
+<input name="CARRYINSEL" num_pins="3"/>
+<input name="INMODE" num_pins="5"/>
+<input name="CEA1" num_pins="1"/>
+<input name="CEA2" num_pins="1"/>
+<input name="CEB1" num_pins="1"/>
+<input name="CEB2" num_pins="1"/>
+<input name="CEC" num_pins="1"/>
+<input name="CED" num_pins="1"/>
+<input name="CEM" num_pins="1"/>
+<input name="CEP" num_pins="1"/>
+<input name="CEAD" num_pins="1"/>
+<input name="CEALUMODE" num_pins="1"/>
+<input name="CECTRL" num_pins="1"/>
+<input name="CECARRYIN" num_pins="1"/>
+<input name="CEINMODE" num_pins="1"/>
+<input name="RSTA" num_pins="1"/>
+<input name="RSTB" num_pins="1"/>
+<input name="RSTC" num_pins="1"/>
+<input name="RSTD" num_pins="1"/>
+<input name="RSTM" num_pins="1"/>
+<input name="RSTP" num_pins="1"/>
+<input name="RSTCTRL" num_pins="1"/>
+<input name="RSTALLCARRYIN" num_pins="1"/>
+<input name="RSTALUMODE" num_pins="1"/>
+<input name="RSTINMODE" num_pins="1"/>
+<input name="ACIN" num_pins="30"/>
+<input name="BCIN" num_pins="18"/>
+<input name="PCIN" num_pins="48"/>
+<input name="CARRYCASCIN" num_pins="1"/>
+<input name="MULTSIGNIN" num_pins="1"/>
+<output name="ACOUT" num_pins="30"/>
+<output name="BCOUT" num_pins="18"/>
+<output name="PCOUT" num_pins="48"/>
+<output name="P" num_pins="48"/>
+<output name="CARRYOUT" num_pins="4"/>
+<output name="CARRYCASCOUT" num_pins="1"/>
+<output name="MULTSIGNOUT" num_pins="1"/>
+<output name="PATTERNDETECT" num_pins="1"/>
+<output name="PATTERNBDETECT" num_pins="1"/>
+<output name="OVERFLOW" num_pins="1"/>
+<output name="UNDERFLOW" num_pins="1"/>
+
+<mode name="DSP">
+<pb_type name="DSP" num_pb="1" blif_model=".subckt DSP48E1_VPR">
+<clock name="CLK" num_pins="1"/>
+
+<input name="A" num_pins="30"/>
+<T_setup value="{setup_CLK_A}" port="A" clock="CLK"/>
+<T_hold value="{hold_CLK_A}" port="A" clock="CLK"/>
+
+<input name="B" num_pins="18"/>
+<T_setup value="{setup_CLK_B}" port="B" clock="CLK"/>
+<T_hold value="{hold_CLK_B}" port="B" clock="CLK"/>
+
+<input name="C" num_pins="48"/>
+<T_setup value="{setup_CLK_C}" port="C" clock="CLK"/>
+<T_hold value="{hold_CLK_C}" port="C" clock="CLK"/>
+
+<input name="D" num_pins="25"/>
+<T_setup value="{setup_CLK_D}" port="D" clock="CLK"/>
+<T_hold value="{hold_CLK_D}" port="D" clock="CLK"/>
+
+<input name="OPMODE" num_pins="7"/>
+<T_setup value="{setup_CLK_OPMODE}" port="OPMODE" clock="CLK"/>
+<T_hold value="{hold_CLK_OPMODE}" port="OPMODE" clock="CLK"/>
+
+<input name="ALUMODE" num_pins="4"/>
+<T_setup value="{setup_CLK_ALUMODE}" port="ALUMODE" clock="CLK"/>
+<T_hold value="{hold_CLK_ALUMODE}" port="ALUMODE" clock="CLK"/>
+
+<input name="CARRYIN" num_pins="1"/>
+<T_setup value="{setup_CLK_CARRYIN}" port="CARRYIN" clock="CLK"/>
+<T_hold value="{hold_CLK_CARRYIN}" port="CARRYIN" clock="CLK"/>
+
+<input name="CARRYINSEL" num_pins="3"/>
+<T_setup value="{setup_CLK_CARRYINSEL}" port="CARRYINSEL" clock="CLK"/>
+<T_hold value="{hold_CLK_CARRYINSEL}" port="CARRYINSEL" clock="CLK"/>
+
+<input name="INMODE" num_pins="5"/>
+<T_setup value="{setup_CLK_INMODE}" port="INMODE" clock="CLK"/>
+<T_hold value="{hold_CLK_INMODE}" port="INMODE" clock="CLK"/>
+
+<input name="CEA1" num_pins="1"/>
+<T_setup value="{setup_CLK_CEA1}" port="CEA1" clock="CLK"/>
+<T_hold value="{hold_CLK_CEA1}" port="CEA1" clock="CLK"/>
+
+<input name="CEA2" num_pins="1"/>
+<T_setup value="{setup_CLK_CEA2}" port="CEA2" clock="CLK"/>
+<T_hold value="{hold_CLK_CEA2}" port="CEA2" clock="CLK"/>
+
+<input name="CEB1" num_pins="1"/>
+<T_setup value="{setup_CLK_CEB1}" port="CEB1" clock="CLK"/>
+<T_hold value="{hold_CLK_CEB1}" port="CEB1" clock="CLK"/>
+
+<input name="CEB2" num_pins="1"/>
+<T_setup value="{setup_CLK_CEB2}" port="CEB2" clock="CLK"/>
+<T_hold value="{hold_CLK_CEB2}" port="CEB2" clock="CLK"/>
+
+<input name="CEC" num_pins="1"/>
+<T_setup value="{setup_CLK_CEC}" port="CEC" clock="CLK"/>
+<T_hold value="{hold_CLK_CEC}" port="CEC" clock="CLK"/>
+
+<input name="CED" num_pins="1"/>
+<T_setup value="{setup_CLK_CED}" port="CED" clock="CLK"/>
+<T_hold value="{hold_CLK_CED}" port="CED" clock="CLK"/>
+
+<input name="CEM" num_pins="1"/>
+<T_setup value="{setup_CLK_CEM}" port="CEM" clock="CLK"/>
+<T_hold value="{hold_CLK_CEM}" port="CEM" clock="CLK"/>
+
+<input name="CEP" num_pins="1"/>
+<T_setup value="{setup_CLK_CEP}" port="CEP" clock="CLK"/>
+<T_hold value="{hold_CLK_CEP}" port="CEP" clock="CLK"/>
+
+<input name="CEAD" num_pins="1"/>
+<T_setup value="{setup_CLK_CEAD}" port="CEAD" clock="CLK"/>
+<T_hold value="{hold_CLK_CEAD}" port="CEAD" clock="CLK"/>
+
+<input name="CEALUMODE" num_pins="1"/>
+<T_setup value="{setup_CLK_CEALUMODE}" port="CEALUMODE" clock="CLK"/>
+<T_hold value="{hold_CLK_CEALUMODE}" port="CEALUMODE" clock="CLK"/>
+
+<input name="CECTRL" num_pins="1"/>
+<T_setup value="{setup_CLK_CECTRL}" port="CECTRL" clock="CLK"/>
+<T_hold value="{hold_CLK_CECTRL}" port="CECTRL" clock="CLK"/>
+
+<input name="CECARRYIN" num_pins="1"/>
+<T_setup value="{setup_CLK_CECARRYIN}" port="CECARRYIN" clock="CLK"/>
+<T_hold value="{hold_CLK_CECARRYIN}" port="CECARRYIN" clock="CLK"/>
+
+<input name="CEINMODE" num_pins="1"/>
+<T_setup value="{setup_CLK_CEINMODE}" port="CEINMODE" clock="CLK"/>
+<T_hold value="{hold_CLK_CEINMODE}" port="CEINMODE" clock="CLK"/>
+
+<input name="RSTA" num_pins="1"/>
+<T_setup value="{setup_CLK_RSTA}" port="RSTA" clock="CLK"/>
+<T_hold value="{hold_CLK_RSTA}" port="RSTA" clock="CLK"/>
+
+<input name="RSTB" num_pins="1"/>
+<T_setup value="{setup_CLK_RSTB}" port="RSTB" clock="CLK"/>
+<T_hold value="{hold_CLK_RSTB}" port="RSTB" clock="CLK"/>
+
+<input name="RSTC" num_pins="1"/>
+<T_setup value="{setup_CLK_RSTC}" port="RSTC" clock="CLK"/>
+<T_hold value="{hold_CLK_RSTC}" port="RSTC" clock="CLK"/>
+
+<input name="RSTD" num_pins="1"/>
+<T_setup value="{setup_CLK_RSTD}" port="RSTD" clock="CLK"/>
+<T_hold value="{hold_CLK_RSTD}" port="RSTD" clock="CLK"/>
+
+<input name="RSTM" num_pins="1"/>
+<T_setup value="{setup_CLK_RSTM}" port="RSTM" clock="CLK"/>
+<T_hold value="{hold_CLK_RSTM}" port="RSTM" clock="CLK"/>
+
+<input name="RSTP" num_pins="1"/>
+<T_setup value="{setup_CLK_RSTP}" port="RSTP" clock="CLK"/>
+<T_hold value="{hold_CLK_RSTP}" port="RSTP" clock="CLK"/>
+
+<input name="RSTCTRL" num_pins="1"/>
+<T_setup value="{setup_CLK_RSTCTRL}" port="RSTCTRL" clock="CLK"/>
+<T_hold value="{hold_CLK_RSTCTRL}" port="RSTCTRL" clock="CLK"/>
+
+<input name="RSTALLCARRYIN" num_pins="1"/>
+<T_setup value="{setup_CLK_RSTALLCARRYIN}" port="RSTALLCARRYIN" clock="CLK"/>
+<T_hold value="{hold_CLK_RSTALLCARRYIN}" port="RSTALLCARRYIN" clock="CLK"/>
+
+<input name="RSTALUMODE" num_pins="1"/>
+<T_setup value="{setup_CLK_RSTALUMODE}" port="RSTALUMODE" clock="CLK"/>
+<T_hold value="{hold_CLK_RSTALUMODE}" port="RSTALUMODE" clock="CLK"/>
+
+<input name="RSTINMODE" num_pins="1"/>
+<T_setup value="{setup_CLK_RSTINMODE}" port="RSTINMODE" clock="CLK"/>
+<T_hold value="{hold_CLK_RSTINMODE}" port="RSTINMODE" clock="CLK"/>
+
+<input name="ACIN" num_pins="30"/>
+<T_setup value="{setup_CLK_ACIN}" port="ACIN" clock="CLK"/>
+<T_hold value="{hold_CLK_ACIN}" port="ACIN" clock="CLK"/>
+
+<input name="BCIN" num_pins="18"/>
+<T_setup value="{setup_CLK_BCIN}" port="BCIN" clock="CLK"/>
+<T_hold value="{hold_CLK_BCIN}" port="BCIN" clock="CLK"/>
+
+<input name="PCIN" num_pins="48"/>
+<T_setup value="{setup_CLK_PCIN}" port="PCIN" clock="CLK"/>
+<T_hold value="{hold_CLK_PCIN}" port="PCIN" clock="CLK"/>
+
+<input name="CARRYCASCIN" num_pins="1"/>
+<T_setup value="{setup_CLK_CARRYCASCIN}" port="CARRYCASCIN" clock="CLK"/>
+<T_hold value="{hold_CLK_CARRYCASCIN}" port="CARRYCASCIN" clock="CLK"/>
+
+<input name="MULTSIGNIN" num_pins="1"/>
+<T_setup value="{setup_CLK_MULTSIGNIN}" port="MULTSIGNIN" clock="CLK"/>
+<T_hold value="{hold_CLK_MULTSIGNIN}" port="MULTSIGNIN" clock="CLK"/>
+
+<output name="ACOUT" num_pins="30"/>
+<T_clock_to_Q max="{iopath_CLK_ACOUT}" port="ACOUT" clock="CLK"/>
+
+<output name="BCOUT" num_pins="18"/>
+<T_clock_to_Q max="{iopath_CLK_BCOUT}" port="BCOUT" clock="CLK"/>
+
+<output name="PCOUT" num_pins="48"/>
+<T_clock_to_Q max="{iopath_CLK_PCOUT}" port="PCOUT" clock="CLK"/>
+
+<output name="P" num_pins="48"/>
+<T_clock_to_Q max="{iopath_CLK_P}" port="P" clock="CLK"/>
+
+<output name="CARRYOUT" num_pins="4"/>
+<T_clock_to_Q max="{iopath_CLK_CARRYOUT}" port="CARRYOUT" clock="CLK"/>
+
+<output name="CARRYCASCOUT" num_pins="1"/>
+<T_clock_to_Q max="{iopath_CLK_CARRYCASCOUT}" port="CARRYCASCOUT" clock="CLK"/>
+
+<output name="MULTSIGNOUT" num_pins="1"/>
+<T_clock_to_Q max="{iopath_CLK_MULTSIGNOUT}" port="MULTSIGNOUT" clock="CLK"/>
+
+<output name="PATTERNDETECT" num_pins="1"/>
+<T_clock_to_Q max="{iopath_CLK_PATTERNDETECT}" port="PATTERNDETECT" clock="CLK"/>
+
+<output name="PATTERNBDETECT" num_pins="1"/>
+<T_clock_to_Q max="{iopath_CLK_PATTERNBDETECT}" port="PATTERNBDETECT" clock="CLK"/>
+
+<output name="OVERFLOW" num_pins="1"/>
+<T_clock_to_Q max="{iopath_CLK_OVERFLOW}" port="OVERFLOW" clock="CLK"/>
+
+<output name="UNDERFLOW" num_pins="1"/>
+<T_clock_to_Q max="{iopath_CLK_UNDERFLOW}" port="UNDERFLOW" clock="CLK"/>
+
+<delay_constant max="{iopath_ACIN_ACOUT}" in_port="ACIN" out_port="ACOUT"/>
+<delay_constant max="{iopath_A_ACOUT}" in_port="A" out_port="ACOUT"/>
+<delay_constant max="{iopath_ACIN_CARRYCASCOUT}" in_port="ACIN" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_ACIN_CARRYOUT}" in_port="ACIN" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_ACIN_MULTSIGNOUT}" in_port="ACIN" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_ACIN_P}" in_port="ACIN" out_port="P"/>
+<delay_constant max="{iopath_ACIN_PATTERNBDETECT}" in_port="ACIN" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_ACIN_PATTERNDETECT}" in_port="ACIN" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_ACIN_PCOUT}" in_port="ACIN" out_port="PCOUT"/>
+<delay_constant max="{iopath_A_CARRYCASCOUT}" in_port="A" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_A_CARRYOUT}" in_port="A" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_A_MULTSIGNOUT}" in_port="A" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_A_P}" in_port="A" out_port="P"/>
+<delay_constant max="{iopath_A_PATTERNBDETECT}" in_port="A" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_A_PATTERNDETECT}" in_port="A" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_A_PCOUT}" in_port="A" out_port="PCOUT"/>
+<delay_constant max="{iopath_D_CARRYCASCOUT}" in_port="D" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_D_CARRYOUT}" in_port="D" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_D_MULTSIGNOUT}" in_port="D" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_D_P}" in_port="D" out_port="P"/>
+<delay_constant max="{iopath_D_PATTERNBDETECT}" in_port="D" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_D_PATTERNDETECT}" in_port="D" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_D_PCOUT}" in_port="D" out_port="PCOUT"/>
+<delay_constant max="{iopath_INMODE_CARRYCASCOUT}" in_port="INMODE" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_INMODE_CARRYOUT}" in_port="INMODE" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_INMODE_MULTSIGNOUT}" in_port="INMODE" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_INMODE_P}" in_port="INMODE" out_port="P"/>
+<delay_constant max="{iopath_INMODE_PATTERNBDETECT}" in_port="INMODE" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_INMODE_PATTERNDETECT}" in_port="INMODE" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_INMODE_PCOUT}" in_port="INMODE" out_port="PCOUT"/>
+<delay_constant max="{iopath_ALUMODE_CARRYCASCOUT}" in_port="ALUMODE" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_ALUMODE_CARRYOUT}" in_port="ALUMODE" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_ALUMODE_MULTSIGNOUT}" in_port="ALUMODE" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_ALUMODE_P}" in_port="ALUMODE" out_port="P"/>
+<delay_constant max="{iopath_ALUMODE_PATTERNBDETECT}" in_port="ALUMODE" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_ALUMODE_PATTERNDETECT}" in_port="ALUMODE" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_ALUMODE_PCOUT}" in_port="ALUMODE" out_port="PCOUT"/>
+<delay_constant max="{iopath_BCIN_BCOUT}" in_port="BCIN" out_port="BCOUT"/>
+<delay_constant max="{iopath_B_BCOUT}" in_port="B" out_port="BCOUT"/>
+<delay_constant max="{iopath_BCIN_CARRYCASCOUT}" in_port="BCIN" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_BCIN_CARRYOUT}" in_port="BCIN" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_BCIN_MULTSIGNOUT}" in_port="BCIN" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_BCIN_P}" in_port="BCIN" out_port="P"/>
+<delay_constant max="{iopath_BCIN_PATTERNBDETECT}" in_port="BCIN" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_BCIN_PATTERNDETECT}" in_port="BCIN" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_BCIN_PCOUT}" in_port="BCIN" out_port="PCOUT"/>
+<delay_constant max="{iopath_B_CARRYCASCOUT}" in_port="B" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_B_CARRYOUT}" in_port="B" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_B_MULTSIGNOUT}" in_port="B" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_B_P}" in_port="B" out_port="P"/>
+<delay_constant max="{iopath_B_PATTERNBDETECT}" in_port="B" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_B_PATTERNDETECT}" in_port="B" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_B_PCOUT}" in_port="B" out_port="PCOUT"/>
+<delay_constant max="{iopath_CARRYIN_CARRYCASCOUT}" in_port="CARRYIN" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_CARRYIN_CARRYOUT}" in_port="CARRYIN" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_CARRYIN_MULTSIGNOUT}" in_port="CARRYIN" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_CARRYIN_P}" in_port="CARRYIN" out_port="P"/>
+<delay_constant max="{iopath_CARRYIN_PATTERNBDETECT}" in_port="CARRYIN" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_CARRYIN_PATTERNDETECT}" in_port="CARRYIN" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_CARRYIN_PCOUT}" in_port="CARRYIN" out_port="PCOUT"/>
+<delay_constant max="{iopath_CARRYINSEL_CARRYCASCOUT}" in_port="CARRYINSEL" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_CARRYINSEL_CARRYOUT}" in_port="CARRYINSEL" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_CARRYINSEL_MULTSIGNOUT}" in_port="CARRYINSEL" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_CARRYINSEL_P}" in_port="CARRYINSEL" out_port="P"/>
+<delay_constant max="{iopath_CARRYINSEL_PATTERNBDETECT}" in_port="CARRYINSEL" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_CARRYINSEL_PATTERNDETECT}" in_port="CARRYINSEL" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_CARRYINSEL_PCOUT}" in_port="CARRYINSEL" out_port="PCOUT"/>
+<delay_constant max="{iopath_C_CARRYCASCOUT}" in_port="C" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_C_CARRYOUT}" in_port="C" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_C_MULTSIGNOUT}" in_port="C" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_C_P}" in_port="C" out_port="P"/>
+<delay_constant max="{iopath_C_PATTERNBDETECT}" in_port="C" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_C_PATTERNDETECT}" in_port="C" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_C_PCOUT}" in_port="C" out_port="PCOUT"/>
+<delay_constant max="{iopath_OPMODE_CARRYCASCOUT}" in_port="OPMODE" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_OPMODE_CARRYOUT}" in_port="OPMODE" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_OPMODE_MULTSIGNOUT}" in_port="OPMODE" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_OPMODE_P}" in_port="OPMODE" out_port="P"/>
+<delay_constant max="{iopath_OPMODE_PATTERNBDETECT}" in_port="OPMODE" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_OPMODE_PATTERNDETECT}" in_port="OPMODE" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_OPMODE_PCOUT}" in_port="OPMODE" out_port="PCOUT"/>
+<delay_constant max="{iopath_CARRYCASCIN_CARRYCASCOUT}" in_port="CARRYCASCIN" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_CARRYCASCIN_CARRYOUT}" in_port="CARRYCASCIN" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_CARRYCASCIN_MULTSIGNOUT}" in_port="CARRYCASCIN" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_CARRYCASCIN_P}" in_port="CARRYCASCIN" out_port="P"/>
+<delay_constant max="{iopath_CARRYCASCIN_PATTERNBDETECT}" in_port="CARRYCASCIN" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_CARRYCASCIN_PATTERNDETECT}" in_port="CARRYCASCIN" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_CARRYCASCIN_PCOUT}" in_port="CARRYCASCIN" out_port="PCOUT"/>
+<delay_constant max="{iopath_MULTSIGNIN_CARRYCASCOUT}" in_port="MULTSIGNIN" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_MULTSIGNIN_CARRYOUT}" in_port="MULTSIGNIN" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_MULTSIGNIN_MULTSIGNOUT}" in_port="MULTSIGNIN" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_MULTSIGNIN_P}" in_port="MULTSIGNIN" out_port="P"/>
+<delay_constant max="{iopath_MULTSIGNIN_PATTERNBDETECT}" in_port="MULTSIGNIN" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_MULTSIGNIN_PATTERNDETECT}" in_port="MULTSIGNIN" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_MULTSIGNIN_PCOUT}" in_port="MULTSIGNIN" out_port="PCOUT"/>
+<delay_constant max="{iopath_PCIN_CARRYCASCOUT}" in_port="PCIN" out_port="CARRYCASCOUT"/>
+<delay_constant max="{iopath_PCIN_CARRYOUT}" in_port="PCIN" out_port="CARRYOUT"/>
+<delay_constant max="{iopath_PCIN_MULTSIGNOUT}" in_port="PCIN" out_port="MULTSIGNOUT"/>
+<delay_constant max="{iopath_PCIN_P}" in_port="PCIN" out_port="P"/>
+<delay_constant max="{iopath_PCIN_PATTERNBDETECT}" in_port="PCIN" out_port="PATTERNBDETECT"/>
+<delay_constant max="{iopath_PCIN_PATTERNDETECT}" in_port="PCIN" out_port="PATTERNDETECT"/>
+<delay_constant max="{iopath_PCIN_PCOUT}" in_port="PCIN" out_port="PCOUT"/>
+
+<!--
+ Fake timing values as there is no database entry for CLOCK TO Q DELAYS of these input pins
+-->
+<T_clock_to_Q max="10e-12" port="A" clock="CLK"/>
+<T_clock_to_Q max="10e-12" port="B" clock="CLK"/>
+<T_clock_to_Q max="10e-12" port="C" clock="CLK"/>
+<T_clock_to_Q max="10e-12" port="D" clock="CLK"/>
+<T_clock_to_Q max="10e-12" port="OPMODE" clock="CLK"/>
+<T_clock_to_Q max="10e-12" port="ALUMODE" clock="CLK"/>
+<T_clock_to_Q max="10e-12" port="INMODE" clock="CLK"/>
+<T_clock_to_Q max="10e-12" port="CARRYIN" clock="CLK"/>
+<T_clock_to_Q max="10e-12" port="CARRYINSEL" clock="CLK"/>
+<T_clock_to_Q max="10e-12" port="ACIN" clock="CLK"/>
+<T_clock_to_Q max="10e-12" port="BCIN" clock="CLK"/>
+<T_clock_to_Q max="10e-12" port="PCIN" clock="CLK"/>
+<T_clock_to_Q max="10e-12" port="CARRYCASCIN" clock="CLK"/>
+<T_clock_to_Q max="10e-12" port="MULTSIGNIN" clock="CLK"/>
+<!--
+ Fake timing values as there is no database entry for SETUP TIMES of these output pins
+-->
+<T_setup value="10e-12" port="ACOUT" clock="CLK"/>
+<T_setup value="10e-12" port="BCOUT" clock="CLK"/>
+<T_setup value="10e-12" port="PCOUT" clock="CLK"/>
+<T_setup value="10e-12" port="P" clock="CLK"/>
+<T_setup value="10e-12" port="CARRYOUT" clock="CLK"/>
+<T_setup value="10e-12" port="CARRYCASCOUT" clock="CLK"/>
+<T_setup value="10e-12" port="MULTSIGNOUT" clock="CLK"/>
+<T_setup value="10e-12" port="PATTERNDETECT" clock="CLK"/>
+<T_setup value="10e-12" port="PATTERNBDETECT" clock="CLK"/>
+<T_setup value="10e-12" port="OVERFLOW" clock="CLK"/>
+<T_setup value="10e-12" port="UNDERFLOW" clock="CLK"/>
+
+<metadata>
+<meta name="fasm_params">
+AREG_0=AREG_0
+AREG_2=AREG_2
+A_INPUT[0]=A_INPUT
+BREG_0=BREG_0
+BREG_2=BREG_2
+B_INPUT[0]=B_INPUT
+MASK[47:0]=MASK
+ZADREG[0]=ADREG
+ZALUMODEREG[0]=ALUMODEREG
+ZAREG_2_ACASCREG_1=ACASCREG
+ZBREG_2_BCASCREG_1=BCASCREG
+ZCARRAYINREG[0]=CARRAYINREG
+ZCARRYINSELREG[0]=CARRYINSELREG
+ZDREG[0]=DREG
+ZINMODEREG[0]=INMODEREG
+ZMREG[0]=MREG
+ZOPMODEREG[0]=OPMODEREG
+ZPREG[0]=PREG
+ZCREG[0]=CREG
+ZIS_ALUMODE_INVERTED[3:0]=IS_ALUMODE_INVERTED
+ZIS_INMODE_INVERTED[4:0]=IS_INMODE_INVERTED
+ZIS_OPMODE_INVERTED[6:0]=IS_OPMODE_INVERTED
+ZIS_CLK_INVERTED=IS_CLK_INVERTED
+ZIS_CARRYIN_INVERTED=IS_CARRYIN_INVERTED
+USE_SIMD_FOUR12_TWO24=USE_SIMD_FOUR12_TWO24
+USE_SIMD_FOUR12=USE_SIMD_FOUR12
+USE_DPORT[0]=USE_DPORT
+SEL_MASK_ROUNDING_MODE1=SEL_MASK_ROUNDING_MODE1
+SEL_MASK_ROUNDING_MODE2=SEL_MASK_ROUNDING_MODE2
+SEL_MASK_C=SEL_MASK_C
+PATTERN[47:0]=PATTERN
+AUTORESET_PATDET_RESET=AUTORESET_PATDET_RESET
+AUTORESET_PATDET_RESET_NOT_MATCH=AUTORESET_PATDET_RESET_NOT_MATCH
+</meta>
+</metadata>
+</pb_type>
+<interconnect>
+<direct name="CLK" input="DSP48.CLK" output="DSP.CLK"/>
+<direct name="A" input="DSP48.A" output="DSP.A"/>
+<direct name="B" input="DSP48.B" output="DSP.B"/>
+<direct name="C" input="DSP48.C" output="DSP.C"/>
+<direct name="D" input="DSP48.D" output="DSP.D"/>
+<direct name="OPMODE" input="DSP48.OPMODE" output="DSP.OPMODE"/>
+<direct name="ALUMODE" input="DSP48.ALUMODE" output="DSP.ALUMODE"/>
+<direct name="CARRYIN" input="DSP48.CARRYIN" output="DSP.CARRYIN"/>
+<direct name="CARRYINSEL" input="DSP48.CARRYINSEL" output="DSP.CARRYINSEL"/>
+<direct name="INMODE" input="DSP48.INMODE" output="DSP.INMODE"/>
+<direct name="CEA1" input="DSP48.CEA1" output="DSP.CEA1"/>
+<direct name="CEA2" input="DSP48.CEA2" output="DSP.CEA2"/>
+<direct name="CEB1" input="DSP48.CEB1" output="DSP.CEB1"/>
+<direct name="CEB2" input="DSP48.CEB2" output="DSP.CEB2"/>
+<direct name="CEC" input="DSP48.CEC" output="DSP.CEC"/>
+<direct name="CED" input="DSP48.CED" output="DSP.CED"/>
+<direct name="CEM" input="DSP48.CEM" output="DSP.CEM"/>
+<direct name="CEP" input="DSP48.CEP" output="DSP.CEP"/>
+<direct name="CEAD" input="DSP48.CEAD" output="DSP.CEAD"/>
+<direct name="CEALUMODE" input="DSP48.CEALUMODE" output="DSP.CEALUMODE"/>
+<direct name="CECTRL" input="DSP48.CECTRL" output="DSP.CECTRL"/>
+<direct name="CECARRYIN" input="DSP48.CECARRYIN" output="DSP.CECARRYIN"/>
+<direct name="CEINMODE" input="DSP48.CEINMODE" output="DSP.CEINMODE"/>
+<direct name="RSTA" input="DSP48.RSTA" output="DSP.RSTA"/>
+<direct name="RSTB" input="DSP48.RSTB" output="DSP.RSTB"/>
+<direct name="RSTC" input="DSP48.RSTC" output="DSP.RSTC"/>
+<direct name="RSTD" input="DSP48.RSTD" output="DSP.RSTD"/>
+<direct name="RSTM" input="DSP48.RSTM" output="DSP.RSTM"/>
+<direct name="RSTP" input="DSP48.RSTP" output="DSP.RSTP"/>
+<direct name="RSTCTRL" input="DSP48.RSTCTRL" output="DSP.RSTCTRL"/>
+<direct name="RSTALLCARRYIN" input="DSP48.RSTALLCARRYIN" output="DSP.RSTALLCARRYIN"/>
+<direct name="RSTALUMODE" input="DSP48.RSTALUMODE" output="DSP.RSTALUMODE"/>
+<direct name="RSTINMODE" input="DSP48.RSTINMODE" output="DSP.RSTINMODE"/>
+<direct name="ACIN" input="DSP48.ACIN" output="DSP.ACIN"/>
+<direct name="BCIN" input="DSP48.BCIN" output="DSP.BCIN"/>
+<direct name="PCIN" input="DSP48.PCIN" output="DSP.PCIN"/>
+<direct name="CARRYCASCIN" input="DSP48.CARRYCASCIN" output="DSP.CARRYCASCIN"/>
+<direct name="MULTSIGNIN" input="DSP48.MULTSIGNIN" output="DSP.MULTSIGNIN"/>
+<direct name="ACOUT" input="DSP.ACOUT" output="DSP48.ACOUT"/>
+<direct name="BCOUT" input="DSP.BCOUT" output="DSP48.BCOUT"/>
+<direct name="PCOUT" input="DSP.PCOUT" output="DSP48.PCOUT"/>
+<direct name="P" input="DSP.P" output="DSP48.P"/>
+<direct name="CARRYOUT" input="DSP.CARRYOUT" output="DSP48.CARRYOUT"/>
+<direct name="CARRYCASCOUT" input="DSP.CARRYCASCOUT" output="DSP48.CARRYCASCOUT"/>
+<direct name="MULTSIGNOUT" input="DSP.MULTSIGNOUT" output="DSP48.MULTSIGNOUT"/>
+<direct name="PATTERNDETECT" input="DSP.PATTERNDETECT" output="DSP48.PATTERNDETECT"/>
+<direct name="PATTERNBDETECT" input="DSP.PATTERNBDETECT" output="DSP48.PATTERNBDETECT"/>
+<direct name="OVERFLOW" input="DSP.OVERFLOW" output="DSP48.OVERFLOW"/>
+<direct name="UNDERFLOW" input="DSP.UNDERFLOW" output="DSP48.UNDERFLOW"/>
+</interconnect>
+</mode>
+</pb_type>
diff --git a/xilinx/common/utils/prjxray_arch_import.py b/xilinx/common/utils/prjxray_arch_import.py
index 3a41f3e..d1a5b8a 100644
--- a/xilinx/common/utils/prjxray_arch_import.py
+++ b/xilinx/common/utils/prjxray_arch_import.py
@@ -521,11 +521,14 @@
"IBUFDS_GTE2": ("Y", 2),
"IPAD": (None, None),
"OPAD": (None, None),
+ "DSP48E1": (None, None),
+ "TIEOFF": (None, None)
}
def make_prefix(site, x, y, from_site_name=False):
""" Make tile FASM prefix for a given site. """
+
if from_site_name:
site_type, _ = site.split('_')
else:
@@ -540,6 +543,8 @@
elif prefix_required[0] == 'XY':
mod_x, mod_y = prefix_required[1]
return site_type, '{}_X{}Y{}'.format(site_type, x % mod_x, y % mod_y)
+ elif site_type == 'DSP48E1':
+ return site_type, '{}.{}_{}'.format("DSP48", "DSP", y % 2)
elif prefix_required[0] is None:
return site_type, None
else:
@@ -607,7 +612,7 @@
(tile_pkey, )
)
- NO_SITE_TYPE_PREFIX = ["SLICEL", "SLICEM", "IBUFDS_GTE2"]
+ NO_SITE_TYPE_PREFIX = ["SLICEL", "SLICEM", "IBUFDS_GTE2", "DSP48E1"]
prefixes = []
diff --git a/xilinx/common/utils/prjxray_db_cache.py b/xilinx/common/utils/prjxray_db_cache.py
index 5d916f8..57d330e 100644
--- a/xilinx/common/utils/prjxray_db_cache.py
+++ b/xilinx/common/utils/prjxray_db_cache.py
@@ -73,6 +73,7 @@
Prints database copy progress.
"""
if self.bar is None:
- self.bar = ProgressBar(max_value=total)
+ self.bar = ProgressBar(maxval=total)
+ self.bar.start()
else:
self.bar.update(total - remaining)
diff --git a/xilinx/common/utils/prjxray_physical_tile_import.py b/xilinx/common/utils/prjxray_physical_tile_import.py
index ca53435..2f2eafe 100755
--- a/xilinx/common/utils/prjxray_physical_tile_import.py
+++ b/xilinx/common/utils/prjxray_physical_tile_import.py
@@ -78,7 +78,6 @@
def add_equivalent_sites(tile_xml, equivalent_sites):
""" Used to add to the <tile> tag the equivalent tiles associated with it."""
-
pb_types = equivalent_sites.split(',')
equivalent_sites_xml = ET.SubElement(tile_xml, 'equivalent_sites')
diff --git a/xilinx/common/utils/prjxray_tile_import.py b/xilinx/common/utils/prjxray_tile_import.py
index 36407bd..312cfc7 100755
--- a/xilinx/common/utils/prjxray_tile_import.py
+++ b/xilinx/common/utils/prjxray_tile_import.py
@@ -373,10 +373,9 @@
for outputs in root_element.iter('output'):
ports[outputs.attrib['name']] = int(outputs.attrib['num_pins'])
-
- assert site_instance not in site_type_ports, (
+ '''assert site_instance not in site_type_ports, (
site_instance, site_type_ports.keys()
- )
+ )'''
site_type_ports[site_instance] = ports
attrib = dict(root_element.attrib)
@@ -1393,7 +1392,7 @@
parser.add_argument('--tile', help="""Tile to generate for""")
parser.add_argument(
- '--site_directory', help="""Diretory where sites are defined"""
+ '--site_directory', help="""Directory where sites are defined"""
)
parser.add_argument(
diff --git a/xilinx/xc7/archs/artix7/devices/xc7a50t-virt/CMakeLists.txt b/xilinx/xc7/archs/artix7/devices/xc7a50t-virt/CMakeLists.txt
index 3848af9..ad60539 100644
--- a/xilinx/xc7/archs/artix7/devices/xc7a50t-virt/CMakeLists.txt
+++ b/xilinx/xc7/archs/artix7/devices/xc7a50t-virt/CMakeLists.txt
@@ -26,6 +26,8 @@
GTP_CHANNEL_2
GTP_CHANNEL_3
PCIE_BOT
+ DSP_L
+ DSP_R
PB_TYPES
SLICEL
SLICEM
@@ -43,4 +45,6 @@
IPAD
OPAD
PCIE_2_1
+ DSP48E1
+ TIEOFF
)
diff --git a/xilinx/xc7/archs/artix7/tiles/CMakeLists.txt b/xilinx/xc7/archs/artix7/tiles/CMakeLists.txt
index b258dc9..fa312d9 100644
--- a/xilinx/xc7/archs/artix7/tiles/CMakeLists.txt
+++ b/xilinx/xc7/archs/artix7/tiles/CMakeLists.txt
@@ -25,6 +25,10 @@
add_subdirectory(mmcme2_adv)
add_subdirectory(cmt_top_l_lower_b)
add_subdirectory(cmt_top_r_lower_b)
+add_subdirectory(dsp_l)
+add_subdirectory(dsp_r)
+add_subdirectory(dsp48e1)
+add_subdirectory(tieoff)
set(IOPAD_SITES IOB33 IDELAYE2 ILOGICE3 OLOGICE3)
set(IOPAD_S_SITES IOB33S IDELAYE2 ILOGICE3 OLOGICE3)
diff --git a/xilinx/xc7/archs/artix7/tiles/dsp48e1/CMakeLists.txt b/xilinx/xc7/archs/artix7/tiles/dsp48e1/CMakeLists.txt
new file mode 100644
index 0000000..39cb5a9
--- /dev/null
+++ b/xilinx/xc7/archs/artix7/tiles/dsp48e1/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+ ARCH artix7
+ TILE DSP48E1
+ SITE_AS_TILE
+ SITE_TYPES DSP48E1/DSP48E1
+ EQUIVALENT_SITES DSP48E1
+ )
diff --git a/xilinx/xc7/archs/artix7/tiles/dsp_l/CMakeLists.txt b/xilinx/xc7/archs/artix7/tiles/dsp_l/CMakeLists.txt
new file mode 100644
index 0000000..b6522ed
--- /dev/null
+++ b/xilinx/xc7/archs/artix7/tiles/dsp_l/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile_capacity(
+ ARCH artix7
+ TILE DSP_L
+ SITE_TYPES DSP48E1/DSP48E1 DSP48E1/DSP48E1 TIEOFF/TIEOFF
+ )
diff --git a/xilinx/xc7/archs/artix7/tiles/dsp_r/CMakeLists.txt b/xilinx/xc7/archs/artix7/tiles/dsp_r/CMakeLists.txt
new file mode 100644
index 0000000..31f2600
--- /dev/null
+++ b/xilinx/xc7/archs/artix7/tiles/dsp_r/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile_capacity(
+ ARCH artix7
+ TILE DSP_R
+ SITE_TYPES DSP48E1/DSP48E1 DSP48E1/DSP48E1 TIEOFF/TIEOFF
+ )
diff --git a/xilinx/xc7/archs/artix7/tiles/tieoff/CMakeLists.txt b/xilinx/xc7/archs/artix7/tiles/tieoff/CMakeLists.txt
new file mode 100644
index 0000000..7361df5
--- /dev/null
+++ b/xilinx/xc7/archs/artix7/tiles/tieoff/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+ ARCH artix7
+ TILE TIEOFF
+ SITE_AS_TILE
+ SITE_TYPES TIEOFF/TIEOFF
+ EQUIVALENT_SITES TIEOFF
+ )
diff --git a/xilinx/xc7/bels.json b/xilinx/xc7/bels.json
index 91b85ca..6b38c04 100644
--- a/xilinx/xc7/bels.json
+++ b/xilinx/xc7/bels.json
@@ -297,5 +297,53 @@
"OLOGICE3_TFF_SAMEEDGE.OLOGICE3"
]
}
+ },
+ "DSP": {
+ "DSP": {
+ "DSP48": [
+ "DSP48E1_ADREG_0_AREG_0_A_INPUT_DIRECT_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_NO_PATDET.DSP48E1",
+ "DSP48E1_BREG_0_B_INPUT_DIRECT_MREG_0_PREG_1_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_NO_PATDET.DSP48E1",
+ "DSP48E1_CREG_0_PREG_1_USE_PATTERN_DETECT_NO_PATDET.DSP48E1",
+ "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_NO_PATDET.DSP48E1",
+ "DSP48E1_OPMODEREG_0_PREG_1_USE_PATTERN_DETECT_NO_PATDET.DSP48E1",
+ "DSP48E1_ALUMODEREG_0_PREG_1_USE_PATTERN_DETECT_NO_PATDET.DSP48E1",
+ "DSP48E1_CARRYINREG_0_PREG_1_USE_PATTERN_DETECT_NO_PATDET.DSP48E1",
+ "DSP48E1_CARRYINSELREG_0_PREG_1_USE_PATTERN_DETECT_NO_PATDET.DSP48E1",
+ "DSP48E1_INMODEREG_0_MREG_0_PREG_1_USE_DPORT_FALSE_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_NO_PATDET.DSP48E1",
+ "DSP48E1_AREG_2.DSP48E1",
+ "DSP48E1_BREG_2.DSP48E1",
+ "DSP48E1_CREG_1.DSP48E1",
+ "DSP48E1_DREG_1.DSP48E1",
+ "DSP48E1_MREG_1.DSP48E1",
+ "DSP48E1_PREG_1.DSP48E1",
+ "DSP48E1_ADREG_1.DSP48E1",
+ "DSP48E1_ALUMODEREG_1.DSP48E1",
+ "DSP48E1_CARRYINSELREG_1.DSP48E1",
+ "DSP48E1_CARRYINREG_1.DSP48E1",
+ "DSP48E1_INMODEREG_1.DSP48E1",
+ "DSP48E1_ADREG_0_AREG_0_A_INPUT_CASCADE_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_MULTIPLY_USE_PATTERN_DETECT_NO_PATDET.DSP48E1",
+ "DSP48E1_BREG_0_B_INPUT_CASCADE_MREG_0_PREG_1_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_NO_PATDET.DSP48E1",
+ "DSP48E1_PREG_1_USE_PATTERN_DETECT_NO_PATDET.DSP48E1",
+ "DSP48E1_ACASCREG_2_AREG_2.DSP48E1",
+ "DSP48E1_BCASCREG_2_BREG_2.DSP48E1",
+ "DSP48E1_BREG_1_MREG_0_PREG_0_USE_MULT_MULTIPLY.DSP48E1",
+ "DSP48E1_ACASCREG_0_A_INPUT_CASCADE.DSP48E1",
+ "DSP48E1_ACASCREG_0_A_INPUT_DIRECT.DSP48E1",
+ "DSP48E1_ADREG_0_AREG_0_A_INPUT_CASCADE_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_MULTIPLY.DSP48E1",
+ "DSP48E1_ADREG_0_AREG_0_A_INPUT_DIRECT_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_MULTIPLY.DSP48E1",
+ "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_MULTIPLY.DSP48E1",
+ "DSP48E1_ADREG_0_INMODEREG_0_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_MULTIPLY.DSP48E1",
+ "DSP48E1_ALUMODEREG_0_PREG_0.DSP48E1",
+ "DSP48E1_BCASCREG_0_B_INPUT_CASCADE.DSP48E1",
+ "DSP48E1_BCASCREG_0_B_INPUT_DIRECT.DSP48E1",
+ "DSP48E1_BREG_0_B_INPUT_CASCADE_MREG_0_PREG_0_USE_MULT_DYNAMIC.DSP48E1",
+ "DSP48E1_BREG_0_B_INPUT_DIRECT_MREG_0_PREG_0_USE_MULT_DYNAMIC.DSP48E1",
+ "DSP48E1_CARRYINREG_0_PREG_0.DSP48E1",
+ "DSP48E1_CARRYINSELREG_0_PREG_0.DSP48E1",
+ "DSP48E1_CREG_0_PREG_0.DSP48E1",
+ "DSP48E1_OPMODEREG_0_PREG_0.DSP48E1",
+ "DSP48E1_PREG_0.DSP48E1"
+ ]
+ }
}
}
diff --git a/xilinx/xc7/techmap/cells_map.v b/xilinx/xc7/techmap/cells_map.v
index 4cc339a..b236f3c 100644
--- a/xilinx/xc7/techmap/cells_map.v
+++ b/xilinx/xc7/techmap/cells_map.v
@@ -10793,3 +10793,324 @@
.USERRSTN(USERRSTN)
);
endmodule
+
+
+module DSP48E1 (
+ output [29:0] ACOUT,
+ output [17:0] BCOUT,
+ output reg CARRYCASCOUT,
+ output reg [3:0] CARRYOUT,
+ output reg MULTSIGNOUT,
+ output OVERFLOW,
+ output reg signed [47:0] P,
+ output reg PATTERNBDETECT,
+ output reg PATTERNDETECT,
+ output [47:0] PCOUT,
+ output UNDERFLOW,
+ input signed [29:0] A,
+ input [29:0] ACIN,
+ input [3:0] ALUMODE,
+ input signed [17:0] B,
+ input [17:0] BCIN,
+ input [47:0] C,
+ input CARRYCASCIN,
+ input CARRYIN,
+ input [2:0] CARRYINSEL,
+ input CEA1,
+ input CEA2,
+ input CEAD,
+ input CEALUMODE,
+ input CEB1,
+ input CEB2,
+ input CEC,
+ input CECARRYIN,
+ input CECTRL,
+ input CED,
+ input CEINMODE,
+ input CEM,
+ input CEP,
+ (* clkbuf_sink *) input CLK,
+ input [24:0] D,
+ input [4:0] INMODE,
+ input MULTSIGNIN,
+ input [6:0] OPMODE,
+ input [47:0] PCIN,
+ input RSTA,
+ input RSTALLCARRYIN,
+ input RSTALUMODE,
+ input RSTB,
+ input RSTC,
+ input RSTCTRL,
+ input RSTD,
+ input RSTINMODE,
+ input RSTM,
+ input RSTP
+);
+ parameter integer ACASCREG = 1;
+ parameter integer ADREG = 1;
+ parameter integer ALUMODEREG = 1;
+ parameter integer AREG = 1;
+ parameter AUTORESET_PATDET = "NO_RESET";
+ parameter A_INPUT = "DIRECT";
+ parameter integer BCASCREG = 1;
+ parameter integer BREG = 1;
+ parameter B_INPUT = "DIRECT";
+ parameter integer CARRYINREG = 1;
+ parameter integer CARRYINSELREG = 1;
+ parameter integer CREG = 1;
+ parameter integer DREG = 1;
+ parameter integer INMODEREG = 1;
+ parameter integer MREG = 1;
+ parameter integer OPMODEREG = 1;
+ parameter integer PREG = 1;
+ parameter SEL_MASK = "MASK";
+ parameter SEL_PATTERN = "PATTERN";
+ parameter USE_DPORT = "FALSE";
+ parameter USE_MULT = "MULTIPLY";
+ parameter USE_PATTERN_DETECT = "NO_PATDET";
+ parameter USE_SIMD = "ONE48";
+ parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
+ parameter [47:0] PATTERN = 48'h000000000000;
+ parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
+ parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [4:0] IS_INMODE_INVERTED = 5'b0;
+ parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
+
+ // DRC CHECKS. See DSP48E1 documentation for more info.
+ // USE_PATTERN_DETECT, USE_MULT AND SEL_PATTERN parameters are always set as their default value as these are not present in the segbits database.
+
+ case (A_INPUT)
+ "DIRECT", "CASCADE" : ;
+ default : begin
+ $error("A_INPUT on DSP48E1 instance is set to an illegal value. Valid options for this parameter are DIRECT or CASCADE");
+ end
+ endcase
+ case (B_INPUT)
+ "DIRECT", "CASCADE" : ;
+ default : begin
+ $error("B_INPUT on DSP48E1 instance is set to an illegal value. Valid options for this parameter are DIRECT or CASCADE");
+ end
+ endcase
+ case (AREG)
+ 0, 1, 2 : ;
+ default : begin
+ $error("AREG on DSP48E1 instance is set to an illegal value. Valid options for this parameter are 0, 1 or 2");
+ end
+ endcase
+ case (AREG)
+ 0 : if(AREG != ACASCREG) begin
+ $error("ACASCREG on DSP48E1 instance is set to an illegal value. ACASCREG has to be set to 0 when AREG is 0");
+ end
+ 1 : if(AREG != ACASCREG) begin
+ $error("ACASCREG on DSP48E1 instance is set to an illegal value. ACASCREG has to be set to 1 when AREG is 1");
+ end
+ 2 : if((AREG != ACASCREG) && ((AREG-1) != ACASCREG)) begin
+ $error("ACASCREG on DSP48E1 instance is set to an illegal value. ACASCREG has to be set to either 2 or 1 when AREG is 2");
+ end
+ default : ;
+ endcase
+ case (BREG)
+ 0, 1, 2 : ;
+ default : begin
+ $error("BREG on DSP48E1 instance is set to an illegal value. Valid options for this parameter are 0, 1 or 2");
+ end
+ endcase
+ case (BREG)
+ 0 : if(BREG != BCASCREG) begin
+ $error("BCASCREG on DSP48E1 instance is set to an illegal value. BCASCREG has to be set to 0 when attribute BREG is 0");
+ end
+ 1 : if(BREG != BCASCREG) begin
+ $error("BCASCREG on DSP48E1 instance is set to an illegal value. BCASCREG has to be set to 1 when attribute BREG is 1");
+ end
+ 2 : if((BREG != BCASCREG) && ((BREG-1) != BCASCREG)) begin
+ $error("BCASCREG on DSP48E1 instance is set to an illegal value. BCASCREG has to be set to either 2 or 1 when attribute BREG is 2");
+ end
+ default : ;
+ endcase
+ case (ALUMODEREG)
+ 0, 1 : ;
+ default : begin
+ $error("ALUMODEREG on DSP48E1 instance is set to an illegal value. Valid options for this parameter are 0 or 1");
+ end
+ endcase
+ case (CARRYINREG)
+ 0, 1 : ;
+ default : begin
+ $error("CARRYINREG on DSP48E1 instance is set to an illegal value. Valid options for this parameter are 0 or 1");
+ end
+ endcase
+ case (CARRYINSELREG)
+ 0, 1 : ;
+ default : begin
+ $error("CARRYINSELREG on DSP48E1 instance is set to an illegal value. Valid options for this parameter are 0 or 1");
+ end
+ endcase
+ case (CREG)
+ 0, 1 : ;
+ default : begin
+ $error("CREG on DSP48E1 instance is set to an illegal value. Valid options for this parameter are 0 or 1");
+ end
+ endcase
+ case (OPMODEREG)
+ 0, 1 : ;
+ default : begin
+ $error("OPMODEREG on DSP48E1 instance is set to an illegal value. Valid options for this parameter are 0 or 1");
+ end
+ endcase
+ case (USE_MULT)
+ "NONE", "MULTIPLY", "DYNAMIC" : ;
+ default : begin
+ $error("USE_MULT on DSP48E1 instance is set to an illegal value. Valid options for this parameter are MULTIPLY, DYNAMIC or NONE");
+ end
+ endcase
+ case (USE_PATTERN_DETECT)
+ "PATDET", "NO_PATDET" : ;
+ default : begin
+ $error("USE_PATTERN_DETECT on DSP48E1 instance is set to an illegal value. Valid options for this parameter are PATDET or NO_PATDET");
+ end
+ endcase
+ case (AUTORESET_PATDET)
+ "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" : ;
+ default : begin
+ $error("AUTORESET_PATDET on DSP48E1 instance is set to an illegal value. Valid options for this parameter are NO_RESET, RESET_MATCH or RESET_NOT_MATCH");
+ end
+ endcase
+ case(SEL_PATTERN)
+ "PATTERN", "C" : ;
+ default : begin
+ $error("SEL_PATTERN on DSP48E1 instance is set to an illegal value. Valid options for this parameter are PATTERN or C");
+ end
+ endcase
+ case(SEL_MASK)
+ "MASK", "C", "ROUNDING_MODE1", "ROUNDING_MODE2" : ;
+ default : begin
+ $error("SEL_MASK on DSP48E1 instance is set to an illegal value. Valid options for this parameter are MASK, C, ROUNDING_MODE1 or ROUNDING_MODE2");
+ end
+ endcase
+ case (MREG)
+ 0, 1 : ;
+ default : begin
+ $error("MREG on DSP48E1 instance is set to an illegal value. Valid options for this parameter are 0 or 1");
+ end
+ endcase
+ case (PREG)
+ 0, 1 : ;
+ default : begin
+ $error("PREG on DSP48E1 instance is set to an illegal value. Valid options for this parameter are 0 or 1");
+ end
+ endcase
+ case (ADREG)
+ 0, 1 : ;
+ default : begin
+ $error("ADREG on DSP48E1 instance is set to an illegal value. Valid options for this parameter are 0 or 1");
+ end
+ endcase
+ case (DREG)
+ 0, 1 : ;
+ default : begin
+ $error("DREG on DSP48E1 instance is set to an illegal value. Valid options for this parameter are 0 or 1");
+ end
+ endcase
+ case (INMODEREG)
+ 0, 1 : ;
+ default : begin
+ $error("INMODEREG on DSP48E1 instance is set to an illegal value. Valid options for this parameter are 0 or 1");
+ end
+ endcase
+ case (USE_DPORT)
+ "TRUE", "FALSE" : ;
+ default : begin
+ $error("USE_DPORT on DSP48E1 instance is set to an illegal value. Valid options for this parameter are TRUE or FALSE");
+ end
+ endcase
+
+ DSP48E1_VPR #(
+
+ .AREG_0(AREG==0),
+ .BREG_0(BREG==0),
+ .AREG_2(AREG==2),
+ .BREG_2(BREG==2),
+ .MASK(MASK),
+ .ADREG(ADREG[0]),
+ .ALUMODEREG(ALUMODEREG[0]),
+ .ACASCREG(AREG==2 && ACASCREG==1),
+ .BCASCREG(BREG==2 && BCASCREG==1),
+ .CARRYINREG(CARRYINREG[0]),
+ .CARRYINSELREG(CARRYINSELREG[0]),
+ .DREG(DREG[0]),
+ .INMODEREG(INMODEREG[0]),
+ .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
+ .IS_INMODE_INVERTED(IS_INMODE_INVERTED),
+ .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED),
+ .MREG(MREG[0]),
+ .OPMODEREG(OPMODEREG[0]),
+ .PREG(PREG[0]),
+ .CREG(CREG[0]),
+ .A_INPUT(A_INPUT == "CASCADE"),
+ .B_INPUT(B_INPUT == "CASCADE"),
+ .USE_DPORT(USE_DPORT == "TRUE"),
+ .USE_SIMD_FOUR12(USE_SIMD == "FOUR12"),
+ .USE_SIMD_FOUR12_TWO24(USE_SIMD == "TWO24"),
+ .AUTORESET_PATDET_RESET(AUTORESET_PATDET == "RESET_MATCH"),
+ .AUTORESET_PATDET_RESET_NOT_MATCH(AUTORESET_PATDET == "RESET_NOT_MATCH"),
+ .PATTERN(PATTERN),
+ .SEL_MASK_ROUNDING_MODE1(SEL_MASK == "ROUNDING_MODE1"),
+ .SEL_MASK_ROUNDING_MODE2(SEL_MASK == "ROUNDING_MODE2"),
+ .SEL_MASK_C(SEL_MASK == "C"),
+ .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
+ .IS_CLK_INVERTED(IS_CLK_INVERTED)
+
+ ) _TECHMAP_REPLACE_ (
+ .ACOUT(ACOUT),
+ .BCOUT(BCOUT),
+ .CARRYCASCOUT(CARRYCASCOUT),
+ .CARRYOUT(CARRYOUT),
+ .MULTSIGNOUT(MULTSIGNOUT),
+ .OVERFLOW(OVERFLOW),
+ .P(P),
+ .PATTERNBDETECT(PATTERNBDETECT),
+ .PATTERNDETECT(PATTERNDETECT),
+ .PCOUT(PCOUT),
+ .UNDERFLOW(UNDERFLOW),
+ .A(A),
+// .ACIN(ACIN),
+ .ALUMODE(ALUMODE),
+ .B(B),
+// .BCIN(BCIN),
+ .C(C),
+// .CARRYCASCIN(CARRYCASCIN),
+ .CARRYIN(CARRYIN),
+ .CARRYINSEL(CARRYINSEL),
+ .CEA1(CEA1),
+ .CEA2(CEA2),
+ .CEAD(CEAD),
+ .CEALUMODE(CEALUMODE),
+ .CEB1(CEB1),
+ .CEB2(CEB2),
+ .CEC(CEC),
+ .CECARRYIN(CECARRYIN),
+ .CECTRL(CECTRL),
+ .CED(CED),
+ .CEINMODE(CEINMODE),
+ .CEM(CEM),
+ .CEP(CEP),
+ .CLK(CLK),
+ .D(D),
+ .INMODE(INMODE),
+// .MULTSIGNIN(MULTSIGNIN),
+ .OPMODE(OPMODE),
+// .PCIN(PCIN),
+ .RSTA(RSTA),
+ .RSTALLCARRYIN(RSTALLCARRYIN),
+ .RSTALUMODE(RSTALUMODE),
+ .RSTB(RSTB),
+ .RSTC(RSTC),
+ .RSTCTRL(RSTCTRL),
+ .RSTD(RSTD),
+ .RSTINMODE(RSTINMODE),
+ .RSTM(RSTM),
+ .RSTP(RSTP)
+ );
+
+endmodule
diff --git a/xilinx/xc7/techmap/cells_sim.v b/xilinx/xc7/techmap/cells_sim.v
index a06ebbe..75994d9 100644
--- a/xilinx/xc7/techmap/cells_sim.v
+++ b/xilinx/xc7/techmap/cells_sim.v
@@ -3575,3 +3575,89 @@
parameter [4:0] VC0_TX_LASTPACKET = 5'd0;
parameter [1:0] CFG_ECRC_ERR_CPLSTAT = 2'd0;
endmodule
+
+module DSP48E1_VPR (
+ input [29:0] A,
+ input [17:0] B,
+ input [47:0] C,
+ input [24:0] D,
+ input [6:0] OPMODE,
+ input [3:0] ALUMODE,
+ input CARRYIN,
+ input [2:0] CARRYINSEL,
+ input [4:0] INMODE,
+ input CEA1,
+ input CEA2,
+ input CEB1,
+ input CEB2,
+ input CEC,
+ input CED,
+ input CEM,
+ input CEP,
+ input CEAD,
+ input CEALUMODE,
+ input CECTRL,
+ input CECARRYIN,
+ input CEINMODE,
+ input RSTA,
+ input RSTB,
+ input RSTC,
+ input RSTD,
+ input RSTM,
+ input RSTP,
+ input RSTCTRL,
+ input RSTALLCARRYIN,
+ input RSTALUMODE,
+ input RSTINMODE,
+ input CLK,
+ input [29:0] ACIN,
+ input [17:0] BCIN,
+ input [47:0] PCIN,
+ input CARRYCASCIN,
+ input MULTSIGNIN,
+ output [29:0] ACOUT,
+ output [17:0] BCOUT,
+ output [47:0] PCOUT,
+ output [47:0] P,
+ output [3:0] CARRYOUT,
+ output CARRYCASCOUT,
+ output MULTSIGNOUT,
+ output PATTERNDETECT,
+ output PATTERNBDETECT,
+ output OVERFLOW,
+ output UNDERFLOW
+);
+ parameter AREG_0 = 1'b0;
+ parameter BREG_0 = 1'b0;
+ parameter AREG_2 = 1'b0;
+ parameter BREG_2 = 1'b0;
+ parameter MASK = 48'b000000000000000000000000000000000000000000000000;
+ parameter PATTERN = 48'b000000000000000000000000000000000000000000000000;
+ parameter ADREG = 1'b0;
+ parameter ALUMODEREG = 1'b0;
+ parameter ACASCREG = 1'b0;
+ parameter BCASCREG = 1'b0;
+ parameter CARRYINREG = 1'b0;
+ parameter CARRYINSELREG = 1'b0;
+ parameter DREG = 1'b0;
+ parameter INMODEREG = 1'b0;
+ parameter MREG = 1'b0;
+ parameter OPMODEREG = 1'b0;
+ parameter PREG = 1'b0;
+ parameter CREG = 1'b0;
+ parameter A_INPUT = 1'b0;
+ parameter B_INPUT = 1'b0;
+ parameter USE_DPORT = 1'b0;
+ parameter USE_SIMD_FOUR12 = 1'b0;
+ parameter USE_SIMD_FOUR12_TWO24 = 1'b0;
+ parameter AUTORESET_PATDET_RESET = 1'b0;
+ parameter AUTORESET_PATDET_RESET_NOT_MATCH = 1'b0;
+ parameter SEL_MASK_ROUNDING_MODE1 = 1'b0;
+ parameter SEL_MASK_ROUNDING_MODE2 = 1'b0;
+ parameter SEL_MASK_C = 1'b0;
+ parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
+ parameter [4:0] IS_INMODE_INVERTED = 5'b0;
+ parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
+ parameter IS_CARRYIN_INVERTED = 1'b0;
+ parameter IS_CLK_INVERTED = 1'b0;
+endmodule
diff --git a/xilinx/xc7/tests/CMakeLists.txt b/xilinx/xc7/tests/CMakeLists.txt
index 4408f5a..244d6f1 100644
--- a/xilinx/xc7/tests/CMakeLists.txt
+++ b/xilinx/xc7/tests/CMakeLists.txt
@@ -45,6 +45,7 @@
add_subdirectory(gtp_channel)
add_subdirectory(pcie)
add_subdirectory(pcie_complex)
+add_subdirectory(dsp)
# Tests with dependencies
set(COUNTER_SRC ${f4pga-arch-defs_SOURCE_DIR}/xilinx/xc7/tests/counter)
diff --git a/xilinx/xc7/tests/dsp/CMakeLists.txt b/xilinx/xc7/tests/dsp/CMakeLists.txt
new file mode 100644
index 0000000..527b4dc
--- /dev/null
+++ b/xilinx/xc7/tests/dsp/CMakeLists.txt
@@ -0,0 +1,9 @@
+add_file_target(FILE dsp.xdc)
+add_file_target(FILE top.v SCANNER_TYPE verilog)
+add_fpga_target(
+ NAME dsp
+ BOARD arty-full
+ SOURCES top.v
+ INPUT_XDC_FILES dsp.xdc
+ EXPLICIT_ADD_FILE_TARGET
+)
diff --git a/xilinx/xc7/tests/dsp/dsp.xdc b/xilinx/xc7/tests/dsp/dsp.xdc
new file mode 100644
index 0000000..e9cae4a
--- /dev/null
+++ b/xilinx/xc7/tests/dsp/dsp.xdc
@@ -0,0 +1,60 @@
+set_property PACKAGE_PIN G16 [get_ports {A[23]}]
+set_property PACKAGE_PIN C17 [get_ports {A[9]}]
+set_property PACKAGE_PIN J17 [get_ports {A[4]}]
+set_property PACKAGE_PIN A15 [get_ports {B[9]}]
+set_property PACKAGE_PIN U14 [get_ports {OUT[6]}]
+set_property PACKAGE_PIN H17 [get_ports {A[14]}]
+set_property PACKAGE_PIN J15 [get_ports {A[1]}]
+set_property PACKAGE_PIN A14 [get_ports {B[6]}]
+set_property PACKAGE_PIN U13 [get_ports {OUT[3]}]
+set_property PACKAGE_PIN C16 [get_ports {A[10]}]
+set_property PACKAGE_PIN U11 [get_ports {OUT[11]}]
+set_property PACKAGE_PIN J13 [get_ports {A[15]}]
+set_property PACKAGE_PIN E18 [get_ports {A[8]}]
+set_property PACKAGE_PIN U17 [get_ports {OUT[16]}]
+set_property PACKAGE_PIN R10 [get_ports {OUT[0]}]
+set_property PACKAGE_PIN E17 [get_ports {A[18]}]
+set_property PACKAGE_PIN K15 [get_ports {A[2]}]
+set_property PACKAGE_PIN D15 [get_ports {B[1]}]
+set_property PACKAGE_PIN V12 [get_ports {OUT[9]}]
+set_property PACKAGE_PIN F15 [get_ports {A[22]}]
+set_property PACKAGE_PIN H14 [get_ports {A[20]}]
+set_property PACKAGE_PIN H15 [get_ports {A[11]}]
+set_property PACKAGE_PIN A18 [get_ports {B[4]}]
+set_property PACKAGE_PIN E15 [get_ports {B[3]}]
+set_property PACKAGE_PIN T10 [get_ports {OUT[1]}]
+set_property PACKAGE_PIN F14 [get_ports {B[14]}]
+set_property PACKAGE_PIN D13 [get_ports {B[12]}]
+set_property PACKAGE_PIN E16 [get_ports {B[2]}]
+set_property PACKAGE_PIN F16 [get_ports {A[21]}]
+set_property PACKAGE_PIN G17 [get_ports {A[13]}]
+set_property PACKAGE_PIN B18 [get_ports {B[5]}]
+set_property PACKAGE_PIN C15 [get_ports {B[0]}]
+set_property PACKAGE_PIN B11 [get_ports {B[17]}]
+set_property PACKAGE_PIN V10 [get_ports {OUT[8]}]
+set_property PACKAGE_PIN K13 [get_ports {A[16]}]
+set_property PACKAGE_PIN D18 [get_ports {A[7]}]
+set_property PACKAGE_PIN B16 [get_ports {B[11]}]
+set_property PACKAGE_PIN V17 [get_ports {OUT[13]}]
+set_property PACKAGE_PIN V11 [get_ports {OUT[7]}]
+set_property PACKAGE_PIN J14 [get_ports {A[12]}]
+set_property PACKAGE_PIN K16 [get_ports {A[0]}]
+set_property PACKAGE_PIN F13 [get_ports {B[15]}]
+set_property PACKAGE_PIN T11 [get_ports {OUT[12]}]
+set_property PACKAGE_PIN D12 [get_ports {B[13]}]
+set_property PACKAGE_PIN G18 [get_ports {A[6]}]
+set_property PACKAGE_PIN U18 [get_ports {OUT[15]}]
+set_property PACKAGE_PIN G14 [get_ports {A[19]}]
+set_property PACKAGE_PIN D17 [get_ports {A[17]}]
+set_property PACKAGE_PIN B17 [get_ports {B[10]}]
+set_property PACKAGE_PIN A16 [get_ports {B[8]}]
+set_property PACKAGE_PIN A13 [get_ports {B[7]}]
+set_property PACKAGE_PIN U16 [get_ports {OUT[14]}]
+set_property PACKAGE_PIN H16 [get_ports {A[24]}]
+set_property PACKAGE_PIN U12 [get_ports {OUT[10]}]
+set_property PACKAGE_PIN F18 [get_ports {A[5]}]
+set_property PACKAGE_PIN V14 [get_ports {OUT[5]}]
+set_property PACKAGE_PIN T13 [get_ports {OUT[4]}]
+set_property PACKAGE_PIN A11 [get_ports {B[16]}]
+set_property PACKAGE_PIN T9 [get_ports {OUT[2]}]
+set_property PACKAGE_PIN J18 [get_ports {A[3]}]
diff --git a/xilinx/xc7/tests/dsp/top.v b/xilinx/xc7/tests/dsp/top.v
new file mode 100644
index 0000000..9ac5341
--- /dev/null
+++ b/xilinx/xc7/tests/dsp/top.v
@@ -0,0 +1,81 @@
+`timescale 1ns / 1ps
+// Structural instantiation of dsp48e1 block in 25x18 multiplier mode using pipelining registers(A1,A2,B1,B2).
+module top
+ (
+ A,
+ B,
+ OUT
+ );
+
+
+ (* IOSTANDARD = "LVCMOS33" *) input wire [24:0] A;
+ (* IOSTANDARD = "LVCMOS33" *) input wire [17:0] B;
+ (* IOSTANDARD = "LVCMOS33" *) output wire [16:0] OUT;
+
+
+ DSP48E1 #(
+ .AREG(2'b10),
+ .BREG(2'b10),
+ .MASK(48'b111110111111101111111111100001111011110111111101),
+ .ADREG(1'b0),
+ .ALUMODEREG(1'b0),
+ .ACASCREG(1'b1),
+ .BCASCREG(1'b1),
+ .CARRYINREG(1'b0),
+ .CARRYINSELREG(1'b0),
+ .DREG(1'b0),
+ .INMODEREG(1'b0),
+ .IS_ALUMODE_INVERTED(4'b1101),
+ .IS_INMODE_INVERTED(5'b11111),
+ .IS_OPMODE_INVERTED(7'b1000101),
+ .MREG(1'b0),
+ .OPMODEREG(1'b0),
+ .PREG(1'b0),
+ .CREG(1'b0),
+ .A_INPUT("CASCADE"),
+ .B_INPUT("CASCADE"),
+ .USE_DPORT("TRUE"),
+ .USE_SIMD("FOUR12"),
+ .AUTORESET_PATDET("RESET_MATCH"),
+ .PATTERN(48'b111110111111101111111111100001111011110111111101),
+ .SEL_MASK("ROUNDING_MODE1"),
+ .IS_CARRYIN_INVERTED(1'b1),
+ .IS_CLK_INVERTED(1'b1)
+ )
+ dsp25x18(
+ .A(A),
+ .ALUMODE(4'b0011),
+ .B(B),
+ .C(48'b111111111111111111111111111111111111111111111111),
+ .CARRYIN(1'b0),
+ .CARRYINSEL(3'b000),
+ .CEA1(1'b1),
+ .CEA2(1'b1),
+ .CEAD(1'b1),
+ .CEALUMODE(1'b1),
+ .CEB1(1'b1),
+ .CEB2(1'b1),
+ .CEC(1'b1),
+ .CECARRYIN(1'b1),
+ .CECTRL(1'b1),
+ .CED(1'b1),
+ .CEINMODE(1'b1),
+ .CEM(1'b1),
+ .CEP(1'b1),
+ .CLK(1'b1),
+ .D(25'b0000000000000000000000000),
+ .INMODE(5'b00000),
+ .OPMODE(7'b0111111),
+ .RSTA(1'b0),
+ .RSTALLCARRYIN(1'b0),
+ .RSTALUMODE(1'b0),
+ .RSTB(1'b0),
+ .RSTC(1'b0),
+ .RSTCTRL(1'b0),
+ .RSTD(1'b0),
+ .RSTINMODE(1'b0),
+ .RSTM(1'b0),
+ .RSTP(1'b0),
+ .P(OUT)
+ );
+endmodule
