xilinx/common/primitives/slicem/srl/srlc32e_vpr.model.xml

<!-- vim: set ai sw=1 ts=1 sta et: -->
<models xmlns:xi="http://www.w3.org/2001/XInclude">
 <model name="SRLC32E_VPR">
  <input_ports>
   <port name="CLK" is_clock="1"/>
   <port name="CE" clock="CLK"/>
   <port name="A" combinational_sink_ports="Q"/>
   <port name="D" clock="CLK"/>
  </input_ports>
  <output_ports>
   <!-- <port name="Q" clock="CLK"/> -->
   <port name="Q"/>
   <port name="Q31" clock="CLK"/>
  </output_ports>
 </model>
</models>