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foss-fpga-tools
/
symbiflow-arch-defs
/
a0714313068f3df09c4cb653f496c837c0fe0cc1
/
.
/
xilinx
/
xc7
/
tests
/
buttons
/
buttons_basys3.v
blob: 36db9e20eff88babbc0a518fea520a826ee8e20a [
file
]
module
top
(
input wire clk
,
input wire rx
,
output wire tx
,
input wire
[
15
:
0
]
sw
,
output wire
[
15
:
0
]
led
);
assign led
=
sw
;
// uart loopback
assign tx
=
rx
;
endmodule