quicklogic/pp3/primitives/vcc/vcc.sim.v - symbiflow-arch-defs - Git at Google

 `timescale 1ps/1ps
 (* whitebox *)
 module VCC (
     output wire VCC
 );

     assign VCC = 1'b1;

 endmodule
	`timescale 1ps/1ps
	(* whitebox *)
	module VCC (
	output wire VCC
	);

	assign VCC = 1'b1;

	endmodule