added vivado target for the dsp test and modified techmaps to produce correct Z-features Signed-off-by: Abhishek Anand <abhishek.anand.nitdgp@gmail.com>
diff --git a/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml b/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml index 45b063e..fde06d2 100644 --- a/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml +++ b/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml
@@ -378,23 +378,23 @@ BREG_2=BREG_2 B_INPUT[0]=B_INPUT MASK[47:0]=MASK -ZADREG[0]=ADREG -ZALUMODEREG[0]=ALUMODEREG -ZAREG_2_ACASCREG_1=ACASCREG -ZBREG_2_BCASCREG_1=BCASCREG -ZCARRAYINREG[0]=CARRAYINREG -ZCARRYINSELREG[0]=CARRYINSELREG -ZDREG[0]=DREG -ZINMODEREG[0]=INMODEREG -ZMREG[0]=MREG -ZOPMODEREG[0]=OPMODEREG -ZPREG[0]=PREG -ZCREG[0]=CREG -ZIS_ALUMODE_INVERTED[3:0]=IS_ALUMODE_INVERTED -ZIS_INMODE_INVERTED[4:0]=IS_INMODE_INVERTED -ZIS_OPMODE_INVERTED[6:0]=IS_OPMODE_INVERTED -ZIS_CLK_INVERTED=IS_CLK_INVERTED -ZIS_CARRYIN_INVERTED=IS_CARRYIN_INVERTED +ZADREG[0]=ZADREG +ZALUMODEREG[0]=ZALUMODEREG +ZAREG_2_ACASCREG_1=ZAREG_2_ACASCREG_1 +ZBREG_2_BCASCREG_1=ZBREG_2_BCASCREG_1 +ZCARRAYINREG[0]=ZCARRAYINREG +ZCARRYINSELREG[0]=ZCARRYINSELREG +ZDREG[0]=ZDREG +ZINMODEREG[0]=ZINMODEREG +ZMREG[0]=ZMREG +ZOPMODEREG[0]=ZOPMODEREG +ZPREG[0]=ZPREG +ZCREG[0]=ZCREG +ZIS_ALUMODE_INVERTED[3:0]=ZIS_ALUMODE_INVERTED +ZIS_INMODE_INVERTED[4:0]=ZIS_INMODE_INVERTED +ZIS_OPMODE_INVERTED[6:0]=ZIS_OPMODE_INVERTED +ZIS_CLK_INVERTED=ZIS_CLK_INVERTED +ZIS_CARRYIN_INVERTED=ZIS_CARRYIN_INVERTED USE_SIMD_FOUR12_TWO24=USE_SIMD_FOUR12_TWO24 USE_SIMD_FOUR12=USE_SIMD_FOUR12 USE_DPORT[0]=USE_DPORT
diff --git a/xilinx/xc7/techmap/cells_map.v b/xilinx/xc7/techmap/cells_map.v index b236f3c..e53b512 100644 --- a/xilinx/xc7/techmap/cells_map.v +++ b/xilinx/xc7/techmap/cells_map.v
@@ -11032,21 +11032,21 @@ .AREG_2(AREG==2), .BREG_2(BREG==2), .MASK(MASK), - .ADREG(ADREG[0]), - .ALUMODEREG(ALUMODEREG[0]), - .ACASCREG(AREG==2 && ACASCREG==1), - .BCASCREG(BREG==2 && BCASCREG==1), - .CARRYINREG(CARRYINREG[0]), - .CARRYINSELREG(CARRYINSELREG[0]), - .DREG(DREG[0]), - .INMODEREG(INMODEREG[0]), - .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED), - .IS_INMODE_INVERTED(IS_INMODE_INVERTED), - .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED), - .MREG(MREG[0]), - .OPMODEREG(OPMODEREG[0]), - .PREG(PREG[0]), - .CREG(CREG[0]), + .ZADREG(~ADREG[0]), + .ZALUMODEREG(~ALUMODEREG[0]), + .ZAREG_2_ACASCREG_1(~(AREG==2 && ACASCREG==1)), + .ZBREG_2_BCASCREG_1(~(BREG==2 && BCASCREG==1)), + .ZCARRYINREG(~CARRYINREG[0]), + .ZCARRYINSELREG(~CARRYINSELREG[0]), + .ZDREG(~DREG[0]), + .ZINMODEREG(~INMODEREG[0]), + .ZIS_ALUMODE_INVERTED(~IS_ALUMODE_INVERTED), + .ZIS_INMODE_INVERTED(~IS_INMODE_INVERTED), + .ZIS_OPMODE_INVERTED(~IS_OPMODE_INVERTED), + .ZMREG(~MREG[0]), + .ZOPMODEREG(~OPMODEREG[0]), + .ZPREG(~PREG[0]), + .ZCREG(~CREG[0]), .A_INPUT(A_INPUT == "CASCADE"), .B_INPUT(B_INPUT == "CASCADE"), .USE_DPORT(USE_DPORT == "TRUE"), @@ -11058,8 +11058,8 @@ .SEL_MASK_ROUNDING_MODE1(SEL_MASK == "ROUNDING_MODE1"), .SEL_MASK_ROUNDING_MODE2(SEL_MASK == "ROUNDING_MODE2"), .SEL_MASK_C(SEL_MASK == "C"), - .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED), - .IS_CLK_INVERTED(IS_CLK_INVERTED) + .ZIS_CARRYIN_INVERTED(~IS_CARRYIN_INVERTED), + .ZIS_CLK_INVERTED(~IS_CLK_INVERTED) ) _TECHMAP_REPLACE_ ( .ACOUT(ACOUT),
diff --git a/xilinx/xc7/techmap/cells_sim.v b/xilinx/xc7/techmap/cells_sim.v index 75994d9..f4c22a7 100644 --- a/xilinx/xc7/techmap/cells_sim.v +++ b/xilinx/xc7/techmap/cells_sim.v
@@ -3633,18 +3633,18 @@ parameter BREG_2 = 1'b0; parameter MASK = 48'b000000000000000000000000000000000000000000000000; parameter PATTERN = 48'b000000000000000000000000000000000000000000000000; - parameter ADREG = 1'b0; - parameter ALUMODEREG = 1'b0; - parameter ACASCREG = 1'b0; - parameter BCASCREG = 1'b0; - parameter CARRYINREG = 1'b0; - parameter CARRYINSELREG = 1'b0; - parameter DREG = 1'b0; - parameter INMODEREG = 1'b0; - parameter MREG = 1'b0; - parameter OPMODEREG = 1'b0; - parameter PREG = 1'b0; - parameter CREG = 1'b0; + parameter ZADREG = 1'b1; + parameter ZALUMODEREG = 1'b1; + parameter ZAREG_2_ACASCREG_1 = 1'b1; + parameter ZBREG_2_BCASCREG_1 = 1'b1; + parameter ZCARRYINREG = 1'b1; + parameter ZCARRYINSELREG = 1'b1; + parameter ZDREG = 1'b1; + parameter ZINMODEREG = 1'b1; + parameter ZMREG = 1'b1; + parameter ZOPMODEREG = 1'b1; + parameter ZPREG = 1'b1; + parameter ZCREG = 1'b1; parameter A_INPUT = 1'b0; parameter B_INPUT = 1'b0; parameter USE_DPORT = 1'b0; @@ -3655,9 +3655,9 @@ parameter SEL_MASK_ROUNDING_MODE1 = 1'b0; parameter SEL_MASK_ROUNDING_MODE2 = 1'b0; parameter SEL_MASK_C = 1'b0; - parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; - parameter [4:0] IS_INMODE_INVERTED = 5'b0; - parameter [6:0] IS_OPMODE_INVERTED = 7'b0; - parameter IS_CARRYIN_INVERTED = 1'b0; - parameter IS_CLK_INVERTED = 1'b0; + parameter [3:0] ZIS_ALUMODE_INVERTED = 4'b1111; + parameter [4:0] ZIS_INMODE_INVERTED = 5'b11111; + parameter [6:0] ZIS_OPMODE_INVERTED = 7'b1111111; + parameter ZIS_CARRYIN_INVERTED = 1'b1; + parameter ZIS_CLK_INVERTED = 1'b1; endmodule
diff --git a/xilinx/xc7/tests/dsp/CMakeLists.txt b/xilinx/xc7/tests/dsp/CMakeLists.txt index 527b4dc..6366775 100644 --- a/xilinx/xc7/tests/dsp/CMakeLists.txt +++ b/xilinx/xc7/tests/dsp/CMakeLists.txt
@@ -1,5 +1,6 @@ add_file_target(FILE dsp.xdc) add_file_target(FILE top.v SCANNER_TYPE verilog) + add_fpga_target( NAME dsp BOARD arty-full @@ -7,3 +8,8 @@ INPUT_XDC_FILES dsp.xdc EXPLICIT_ADD_FILE_TARGET ) + +add_vivado_target( + NAME dsp_vivado + PARENT_NAME dsp +)
diff --git a/xilinx/xc7/tests/dsp/dsp.xdc b/xilinx/xc7/tests/dsp/dsp.xdc index e9cae4a..77f8e0f 100644 --- a/xilinx/xc7/tests/dsp/dsp.xdc +++ b/xilinx/xc7/tests/dsp/dsp.xdc
@@ -58,3 +58,4 @@ set_property PACKAGE_PIN A11 [get_ports {B[16]}] set_property PACKAGE_PIN T9 [get_ports {OUT[2]}] set_property PACKAGE_PIN J18 [get_ports {A[3]}] +set_property PACKAGE_PIN A9 [get_ports {Cin}]
diff --git a/xilinx/xc7/tests/dsp/top.v b/xilinx/xc7/tests/dsp/top.v index 9ac5341..daa7a47 100644 --- a/xilinx/xc7/tests/dsp/top.v +++ b/xilinx/xc7/tests/dsp/top.v
@@ -4,15 +4,17 @@ ( A, B, + Cin, OUT ); - - + + (* IOSTANDARD = "LVCMOS33" *) input wire [24:0] A; (* IOSTANDARD = "LVCMOS33" *) input wire [17:0] B; + (* IOSTANDARD = "LVCMOS33" *) input wire Cin; (* IOSTANDARD = "LVCMOS33" *) output wire [16:0] OUT; - + DSP48E1 #( .AREG(2'b10), .BREG(2'b10), @@ -25,9 +27,9 @@ .CARRYINSELREG(1'b0), .DREG(1'b0), .INMODEREG(1'b0), - .IS_ALUMODE_INVERTED(4'b1101), - .IS_INMODE_INVERTED(5'b11111), - .IS_OPMODE_INVERTED(7'b1000101), + .IS_ALUMODE_INVERTED(4'b0000), + .IS_INMODE_INVERTED(5'b00000), + .IS_OPMODE_INVERTED(7'b00000), .MREG(1'b0), .OPMODEREG(1'b0), .PREG(1'b0), @@ -35,34 +37,33 @@ .A_INPUT("CASCADE"), .B_INPUT("CASCADE"), .USE_DPORT("TRUE"), - .USE_SIMD("FOUR12"), .AUTORESET_PATDET("RESET_MATCH"), .PATTERN(48'b111110111111101111111111100001111011110111111101), .SEL_MASK("ROUNDING_MODE1"), - .IS_CARRYIN_INVERTED(1'b1), - .IS_CLK_INVERTED(1'b1) + .IS_CARRYIN_INVERTED(1'b0), + .IS_CLK_INVERTED(1'b1) ) dsp25x18( .A(A), .ALUMODE(4'b0011), .B(B), - .C(48'b111111111111111111111111111111111111111111111111), - .CARRYIN(1'b0), - .CARRYINSEL(3'b000), - .CEA1(1'b1), - .CEA2(1'b1), - .CEAD(1'b1), - .CEALUMODE(1'b1), - .CEB1(1'b1), - .CEB2(1'b1), - .CEC(1'b1), - .CECARRYIN(1'b1), - .CECTRL(1'b1), - .CED(1'b1), - .CEINMODE(1'b1), - .CEM(1'b1), - .CEP(1'b1), - .CLK(1'b1), + .C(48'b111111111111111111111111111111111111111111111111), + .CARRYIN(Cin), + .CARRYINSEL(3'b000), + .CEA1(1'b1), + .CEA2(1'b1), + .CEAD(1'b1), + .CEALUMODE(1'b1), + .CEB1(1'b1), + .CEB2(1'b1), + .CEC(1'b1), + .CECARRYIN(1'b1), + .CECTRL(1'b1), + .CED(1'b1), + .CEINMODE(1'b1), + .CEM(1'b1), + .CEP(1'b1), + .CLK(1'b1), .D(25'b0000000000000000000000000), .INMODE(5'b00000), .OPMODE(7'b0111111),