xilinx/common/primitives/bram/ramb18e1.model.xml

<!-- vim: set ai sw=1 ts=1 sta et: -->
<models>
 <model name="RAMB18E1_VPR">
  <input_ports>
   <!-- Port A - 16bit wide -->
   <port is_clock="1"        name="CLKARDCLK"     />
   <port clock="CLKARDCLK"   name="ENARDEN"       />
   <port clock="CLKARDCLK"   name="REGCEAREGCE"   />
   <port clock="CLKARDCLK"   name="REGCLKARDRCLK" />
   <port clock="CLKARDCLK"   name="RSTRAMARSTRAM" />
   <port clock="CLKARDCLK"   name="RSTREGARSTREG" />
   <port                     name="ADDRATIEHIGH"  />
   <port clock="CLKARDCLK"   name="ADDRARDADDR"   />
   <port clock="CLKARDCLK"   name="DIADI"         />
   <port clock="CLKARDCLK"   name="DIPADIP"       />
   <port clock="CLKARDCLK"   name="WEA"           />

   <!-- Port B - 16bit wide -->
   <port is_clock="1"        name="CLKBWRCLK"     />
   <port clock="CLKBWRCLK"   name="ENBWREN"       />
   <port clock="CLKBWRCLK"   name="REGCLKB"       />
   <port clock="CLKBWRCLK"   name="REGCEB"        />
   <port clock="CLKBWRCLK"   name="RSTRAMB"       />
   <port clock="CLKBWRCLK"   name="RSTREGB"       />
   <port                     name="ADDRBTIEHIGH"  />
   <port clock="CLKBWRCLK"   name="ADDRBWRADDR"   />
   <port clock="CLKBWRCLK"   name="DIBDI"         />
   <port clock="CLKBWRCLK"   name="DIPBDIP"       />
   <port clock="CLKBWRCLK"   name="WEBWE"         />
  </input_ports>
  <output_ports>
   <!-- Port A - 16bit wide -->
   <port clock="CLKARDCLK" name="DOADO"   />
   <port clock="CLKARDCLK" name="DOPADOP" />

   <!-- Port B - 16bit wide -->
   <port clock="CLKBWRCLK" name="DOBDO"   />
   <port clock="CLKBWRCLK" name="DOPBDOP" />
  </output_ports>
 </model>
</models>