lattice/ice40/primitives/sb_ram/sb_ram.model.xml

<!-- set: ai sw=1 ts=1 sta et -->
 <models>
  <model name="SB_RAM40_4K">
    <input_ports>
      <!-- Read port -->
      <port name="RCLK"  is_clock="1"/>
      <port name="RCLKE" clock="RCLK" combinational_sink_ports="RDATA"/>
      <port name="RE"    clock="RCLK" combinational_sink_ports="RDATA"/>
      <port name="RADDR" clock="RCLK" combinational_sink_ports="RDATA"/>
      <!-- Write port -->
      <port name="WCLK"  is_clock="1"/>
      <port name="WCLKE" clock="WCLK" combinational_sink_ports="RDATA"/>
      <port name="WE"    clock="WCLK" combinational_sink_ports="RDATA"/>
      <port name="WADDR" clock="WCLK" combinational_sink_ports="RDATA"/>
      <port name="MASK"  clock="WCLK" combinational_sink_ports="RDATA"/>
      <port name="WDATA" clock="WCLK" combinational_sink_ports="RDATA"/>
    </input_ports>
    <output_ports>
      <port name="RDATA" clock="RCLK"/>
    </output_ports>
  </model>
 </models>