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foss-fpga-tools
/
symbiflow-arch-defs
/
refs/heads/bot-conda-lock-update
/
.
/
quicklogic
/
pp3
/
tests
/
ext_mult
/
ext_mult.v
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module
top
(
input wire
[
7
:
0
]
dat_a
,
input wire
[
7
:
0
]
dat_b
,
output wire
[
15
:
0
]
dat_o
);
// Asynchronous multiplier implemented using logic.
// For the purpose of timing model evaluation.
assign dat_o
=
dat_a
*
dat_b
;
endmodule