testarch/devices/test2/arch.xml

<!-- set: ai sw=1 ts=1 sta et -->
<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
 <models>
  <xi:include href="../../tiles/lutff3/lutff3.model.xml" xpointer="xpointer(models/child::node())" />
 </models>

 <!-- Layout of the FPGA, we are using 4x4 -->
 <layout>
  <fixed_layout name="2x4" width="9" height="6">

   <col type="EMPTY"   startx="0" priority="10" />
   <col type="VPR_PAD" startx="1" priority="10" />
   <col type="EMPTY"   startx="2" priority="10" />

   <col type="TILE"    startx="3" priority="10" />
   <col type="TILE"    startx="4" priority="10" />
   <col type="TILE"    startx="5" priority="10" />

   <col type="EMPTY"   startx="6" priority="10" />
   <col type="VPR_PAD" startx="7" priority="10" />
   <col type="EMPTY"   startx="8" priority="10" />

   <row type="EMPTY"   starty="0" priority="11" />
   <row type="EMPTY"   starty="5" priority="11" />

  </fixed_layout>
 </layout>

 <device>
    <sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000" />
    <area grid_logic_tile_area="14813.392"/>
    <connection_block input_switch_name="1"/>
    <switch_block type="wilton" fs="3"/>
    <chan_width_distr>
      <x distr="uniform" peak="1.000000"/>
      <y distr="uniform" peak="1.000000"/>
    </chan_width_distr>
 </device>

 <switchlist>
  <switch type="mux" name="1" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
 </switchlist>
 <segmentlist>
  <segment name="segment" length="4" freq="0.750000" type="unidir" Rmetal="101" Cmetal="22.5e-15">
   <sb type="pattern">1 1 1 1 1</sb>
   <cb type="pattern">1 1 1 1</cb>
   <mux name="1"/>
   <wire_switch name="1"/>
   <opin_switch name="1"/>
  </segment>
 </segmentlist>
 <complexblocklist>
  <xi:include href="../../../vpr/pad/pad.pb_type.xml"/>
  <xi:include href="../../tiles/lutff3/lutff3.pb_type.xml"/>
 </complexblocklist>

 <directlist>
  <!-- Top inputs -->
  <direct name="00" from_pin="TILE.OUT[3:3]" to_pin="TILE.IN[2:2]"   x_offset="-1" y_offset="-1" z_offset="0"/>
  <direct name="01" from_pin="TILE.OUT[3:3]" to_pin="TILE.IN[1:1]"   x_offset="0"  y_offset="-1" z_offset="0"/>
  <direct name="02" from_pin="TILE.OUT[3:3]" to_pin="TILE.IN[0:0]"   x_offset="1"  y_offset="-1" z_offset="0"/>

  <!-- Right inputs -->
  <direct name="03" from_pin="TILE.OUT[1:1]" to_pin="TILE.IN[8:8]"   x_offset="1"  y_offset="-1" z_offset="0"/>
  <direct name="04" from_pin="TILE.OUT[1:1]" to_pin="TILE.IN[7:7]"   x_offset="1"  y_offset="0"  z_offset="0"/>
  <direct name="05" from_pin="TILE.OUT[1:1]" to_pin="TILE.IN[6:6]"   x_offset="1"  y_offset="1"  z_offset="0"/>

  <!-- Bottom inputs -->
  <direct name="06" from_pin="TILE.OUT[0:0]" to_pin="TILE.IN[11:11]" x_offset="-1" y_offset="1"  z_offset="0"/>
  <direct name="07" from_pin="TILE.OUT[0:0]" to_pin="TILE.IN[10:10]" x_offset="0"  y_offset="1"  z_offset="0"/>
  <direct name="08" from_pin="TILE.OUT[0:0]" to_pin="TILE.IN[9:9]"   x_offset="1"  y_offset="1"  z_offset="0"/>

  <!-- Left inputs -->
  <direct name="09" from_pin="TILE.OUT[2:2]" to_pin="TILE.IN[5:5]"   x_offset="-1" y_offset="-1" z_offset="0"/>
  <direct name="10" from_pin="TILE.OUT[2:2]" to_pin="TILE.IN[4:4]"   x_offset="-1" y_offset="0"  z_offset="0"/>
  <direct name="11" from_pin="TILE.OUT[2:2]" to_pin="TILE.IN[3:3]"   x_offset="-1" y_offset="1"  z_offset="0"/>

 </directlist>
</architecture>