xilinx/common/primitives/bram/rambfifo36e1.model.xml

<!-- vim: set ai sw=1 ts=1 sta et: -->
<models>
 <model name="RAMB36E1_PRIM">
  <input_ports>
   <!-- Port A - 32bit wide -->
   <port is_clock="1"        name="CLKARDCLKU"     />
   <port is_clock="1"        name="CLKARDCLKL"     />
   <port clock="CLKARDCLKL"   name="ENARDENU"       />
   <port clock="CLKARDCLKL"   name="ENARDENL"       />
   <port clock="CLKARDCLKL"   name="REGCEAREGCEU"   />
   <port clock="CLKARDCLKL"   name="REGCEAREGCEL"   />
   <port clock="CLKARDCLKL"   name="REGCLKARDRCLKU" />
   <port clock="CLKARDCLKL"   name="REGCLKARDRCLKL" />
   <port clock="CLKARDCLKL"   name="RSTRAMARSTRAMU" />
   <port clock="CLKARDCLKL"   name="RSTRAMARSTRAMLRST" />
   <port clock="CLKARDCLKL"   name="RSTREGARSTREGU" />
   <port clock="CLKARDCLKL"   name="RSTREGARSTREGL" />
   <port clock="CLKARDCLKL"   name="ADDRARDADDRU"   />
   <port clock="CLKARDCLKL"   name="ADDRARDADDRL"   />
   <port clock="CLKARDCLKL"   name="DIADI"         />
   <port clock="CLKARDCLKL"   name="DIPADIP"       />
   <port clock="CLKARDCLKL"   name="WEAU"           />
   <port clock="CLKARDCLKL"   name="WEAL"           />

   <!-- Port B - 32bit wide -->
   <port is_clock="1"        name="CLKBWRCLKU"     />
   <port is_clock="1"        name="CLKBWRCLKL"     />
   <port clock="CLKBWRCLKL"   name="ENBWRENU"       />
   <port clock="CLKBWRCLKL"   name="ENBWRENL"       />
   <port clock="CLKBWRCLKL"   name="REGCEBU"        />
   <port clock="CLKBWRCLKL"   name="REGCEBL"        />
   <port clock="CLKBWRCLKL"   name="REGCLKBU"       />
   <port clock="CLKBWRCLKL"   name="REGCLKBL"       />
   <port clock="CLKBWRCLKL"   name="RSTRAMBU"       />
   <port clock="CLKBWRCLKL"   name="RSTRAMBL"       />
   <port clock="CLKBWRCLKL"   name="RSTREGBU"       />
   <port clock="CLKBWRCLKL"   name="RSTREGBL"       />
   <port clock="CLKBWRCLKL"   name="ADDRBWRADDRU"   />
   <port clock="CLKBWRCLKL"   name="ADDRBWRADDRL"   />
   <port clock="CLKBWRCLKL"   name="DIBDI"         />
   <port clock="CLKBWRCLKL"   name="DIPBDIP"       />
   <port clock="CLKBWRCLKL"   name="WEBWEU"         />
   <port clock="CLKBWRCLKL"   name="WEBWEL"         />

   <!-- FIXME -->
   <port  name="CASCADEINA"    />
   <port  name="CASCADEINB"    />
  </input_ports>
  <output_ports>
   <!-- Port A - 32bit wide -->
   <port clock="CLKARDCLKL" name="DOADO"   />
   <port clock="CLKARDCLKL" name="DOPADOP" />

   <!-- Port B - 32bit wide -->
   <port clock="CLKBWRCLKL" name="DOBDO"   />
   <port clock="CLKBWRCLKL" name="DOPBDOP" />

   <!-- FIXME -->
   <port name="CASCADEOUTA"   />
   <port name="CASCADEOUTB"   />
  </output_ports>
 </model>
</models>