xilinx/common/primitives/ff/ff.model.xml

<models>
  <model name="FDRE_ZINI">
    <input_ports>
      <port name="C"  is_clock="1" />
      <port name="CE" clock="C" />
      <port name="R"  clock="C" />
      <port name="D"  clock="C" />
    </input_ports>
    <output_ports>
      <port name="Q"  clock="C" />
    </output_ports>
  </model>
  <model name="FDSE_ZINI">
    <input_ports>
      <port name="C"  is_clock="1" />
      <port name="CE" clock="C" />
      <port name="S"  clock="C" />
      <port name="D"  clock="C" />
    </input_ports>
    <output_ports>
      <port name="Q"  clock="C" />
    </output_ports>
  </model>
  <model name="FDPE_ZINI">
    <input_ports>
      <port name="C"   is_clock="1" />
      <port name="CE"  clock="C" />
      <port name="PRE" clock="C" />
      <port name="D"   clock="C" />
    </input_ports>
    <output_ports>
      <port name="Q"   clock="C" />
    </output_ports>
  </model>
  <model name="FDCE_ZINI">
    <input_ports>
      <port name="C"   is_clock="1" />
      <port name="CE"  clock="C" />
      <port name="CLR" clock="C" />
      <port name="D"   clock="C" />
    </input_ports>
    <output_ports>
      <port name="Q"   clock="C"  />
    </output_ports>
  </model>
  <model name="LDPE_ZINI">
    <input_ports>
      <port name="G"   combinational_sink_ports="Q" is_clock="1" />
      <port name="GE"  combinational_sink_ports="Q" />
      <port name="PRE" combinational_sink_ports="Q" />
      <port name="D"   clock="G" />
    </input_ports>
    <output_ports>
      <port name="Q" />
    </output_ports>
  </model>
  <model name="LDCE_ZINI">
    <input_ports>
      <port name="G"   combinational_sink_ports="Q" is_clock="1" />
      <port name="GE"  combinational_sink_ports="Q" />
      <port name="CLR" combinational_sink_ports="Q" />
      <port name="D"   clock="G" />
    </input_ports>
    <output_ports>
      <port name="Q" />
    </output_ports>
  </model>
  <model name="NO_FF">
    <input_ports>
      <port name="D" />
    </input_ports>
  </model>
</models>