xilinx/common/primitives/idelayctrl/idelayctrl.model.xml

<models>
  <model name="IDELAYCTRL" never_prune="true">
    <input_ports>
      <!-- synchronous control inputs -->
      <port is_clock="1" name="REFCLK"/>
      <port name="RST"/>
    </input_ports>
    <output_ports>
      <port name="RDY"/>
    </output_ports>
  </model>
</models>