| <models xmlns:xi="http://www.w3.org/2001/XInclude"> |
| <model name="OSERDESE2_VPR"> |
| <input_ports> |
| <port is_clock="1" name="CLK"/> |
| <port is_clock="1" name="CLKDIV"/> |
| <port clock="CLKDIV" name="D1"/> |
| <port clock="CLKDIV" name="D2"/> |
| <port clock="CLKDIV" name="D3"/> |
| <port clock="CLKDIV" name="D4"/> |
| <port clock="CLKDIV" name="D5"/> |
| <port clock="CLKDIV" name="D6"/> |
| <port clock="CLKDIV" name="D7"/> |
| <port clock="CLKDIV" name="D8"/> |
| <port clock="CLK" name="OCE"/> |
| <port clock="CLKDIV" name="RST"/> |
| <port clock="CLKDIV" combinational_sink_ports="TBYTEOUT" name="T1"/> |
| <port clock="CLKDIV" name="T2"/> |
| <port clock="CLKDIV" name="T3"/> |
| <port clock="CLKDIV" name="T4"/> |
| <port name="TBYTEIN"/> |
| <port clock="CLK" name="TCE"/> |
| <port name="SHIFTIN1"/> |
| <port name="SHIFTIN2"/> |
| </input_ports> |
| <output_ports> |
| <port clock="CLKDIV" name="IOCLKGLITCH"/> |
| <port clock="CLK" name="OFB"/> |
| <port clock="CLK" name="OQ"/> |
| <port name="SHIFTOUT1"/> |
| <port name="SHIFTOUT2"/> |
| <port name="TBYTEOUT"/> |
| <port clock="CLK" name="TFB"/> |
| <port clock="CLK" name="TQ"/> |
| </output_ports> |
| </model> |
| <model name="ODDR_VPR"> |
| <input_ports> |
| <port name="CK" is_clock="1"/> |
| <port name="CE" clock="CK"/> |
| <port name="SR"/> |
| <port name="D1" clock="CK"/> |
| <port name="D2" clock="CK"/> |
| </input_ports> |
| <output_ports> |
| <port name="Q" clock="CK"/> |
| </output_ports> |
| </model> |
| <model name="T_INV"> |
| <input_ports> |
| <port name="TI" combinational_sink_ports="TO"/> |
| </input_ports> |
| <output_ports> |
| <port name="TO"/> |
| </output_ports> |
| </model> |
| </models> |