xilinx/common/primitives/slicem/Ndram/ntemplate.N_dram.model.xml

<!-- vim: set ai sw=1 ts=1 sta et: -->
<models xmlns:xi="http://www.w3.org/2001/XInclude">
 <xi:include href="../../common_slice/Nlut/ntemplate.Nlut.model.xml" xpointer="xpointer(models/child::node())"/>
 <model name="NO_DRAM">
  <input_ports>
   <port                name="A" />
  </input_ports>
  <output_ports/>
 </model>
 <model name="DPRAM64_for_RAM128X1D">
  <input_ports>
   <port is_clock="1"   name="CLK" />
   <port clock="CLK"    name="WE"  />
   <port clock="CLK"    name="DI"  />
   <port clock="CLK"    name="WA"  />
   <port clock="CLK"    name="WA7" />

   <port                name="A"   combinational_sink_ports="O" />
  </input_ports>
  <output_ports>
   <port                name="O" />
  </output_ports>
 </model>
 <model name="DPRAM64">
  <input_ports>
   <port is_clock="1"   name="CLK" />
   <port clock="CLK"    name="WE"  />
   <port clock="CLK"    name="DI"  />
   <port clock="CLK"    name="WA"  />
   <port clock="CLK"    name="WA7" />
   <port clock="CLK"    name="WA8" />

   <port                name="A"   combinational_sink_ports="O" />
  </input_ports>
  <output_ports>
   <port                name="O" />
  </output_ports>
 </model>
 <model name="DPRAM32">
  <input_ports>
   <port is_clock="1"   name="CLK" />
   <port clock="CLK"    name="WE"  />
   <port clock="CLK"    name="DI"  />
   <port clock="CLK"    name="WA"  />

   <port                name="A"   combinational_sink_ports="O" />
  </input_ports>
  <output_ports>
   <port                name="O" />
  </output_ports>
 </model>
 <model name="SPRAM32">
  <input_ports>
   <port is_clock="1"   name="CLK" />
   <port clock="CLK"    name="WE"  />
   <port clock="CLK"    name="DI"  />
   <port clock="CLK"    name="WA"  />

   <port                name="A"   combinational_sink_ports="O" />
  </input_ports>
  <output_ports>
   <port                name="O" />
  </output_ports>
 </model>
</models>