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foss-fpga-tools
/
symbiflow-arch-defs
/
refs/heads/bot-conda-lock-update
/
.
/
xilinx
/
xc7
/
tests
/
buttons
/
buttons_basys3_full.v
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module
top
(
input wire clk
,
input wire
[
15
:
0
]
sw
,
output wire
[
15
:
0
]
led
,
input wire rx
,
output wire tx
);
assign led
=
sw
;
endmodule