blob: 6e0cd5b434f7e4dae0867c76fde79c55af92f2b7 [file] [log] [blame] [edit]
module top (
input wire clk,
output wire [3:0] led
);
localparam BITS = 8;
localparam LOG2DELAY = 18;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led = counter >> LOG2DELAY;
endmodule